1. March 6, 200739th Southeastern Symposium on System Theory1 Transition Delay Fault Testing of Microprocessors by Spectral Method Nitin Yogi and Vishwani D. Agrawal Auburn University Department of ECE Auburn, AL 36849, USA

2. March 6, 200739th Southeastern Symposium on System Theory2 Outline Introduction  Defects and transition delay fault model  Microprocessor testing Issues Problem and Approach  Register-transfer level modeling of transition delay faults  Spectral analysis and test generation Design for Testability Experimental Results Conclusion

3. March 6, 200739th Southeastern Symposium on System Theory3 An Open Circuit Defect Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages 173-180.

4. March 6, 200739th Southeastern Symposium on System Theory4 A Bridging Defect Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages 173-180.

5. March 6, 200739th Southeastern Symposium on System Theory5 A Possible Delay Defect Reference: W. Maly, “Realistic Fault Modeling for VLSI Testing”, Proceedings of the 24th ACM/IEEE Design Automation Conference, 1987, Miami Beach, Florida, Pages 173-180.

6. March 6, 200739th Southeastern Symposium on System Theory6 Stuck-at Fault Model Stuck-at 0 A B C Y Fault activated Fault detected

7. March 6, 200739th Southeastern Symposium on System Theory7 Transition (Delay) Fault Model Slow-to-rise fault A B C Y Fault activated Fault detected

8. March 6, 200739th Southeastern Symposium on System Theory8 Microprocessor Testing Issues Issues arising from Increased Design Complexity Increased Demands on Testing  A Viable Test Method: Functional at-speed tests Advantages: easy to derive; cover many defects Disadvantages: Long test sequences; full coverage not guaranteed  Need Fault-Oriented Test Generation Methods Test pattern generators work at gate level Have very high complexity RTL Test Generation  Advantages: Low testing complexity Early detection of testability issues

9. March 6, 200739th Southeastern Symposium on System Theory9 Problem and Approach The problem is …  Develop an RTL ATPG method to generate functional at-speed tests. And our approach is …  Circuit characterization using RTL: RTL test generation Analysis of information content and noise in RTL vectors.  Test generation for gate-level implementation: Generation of spectral vectors Fault simulation and vector compaction

10. March 6, 200739th Southeastern Symposium on System Theory10 Faults Modeled at Register-Transfer Level Combinational Logic FF Inputs Outputs RTL transition delay fault sites A circuit is an interconnect of several RTL modules. RTL modules

11. March 6, 200739th Southeastern Symposium on System Theory11 Analyzing Bit-Streams of RTL Tests 0 to -1 Bit-stream Vector 1 Vector 2. Input 1 Input 2. Bit-stream of Input 2

12. March 6, 200739th Southeastern Symposium on System Theory12 Spectral Characterization of a Bit-Stream Bit stream to analyze Correlating with Walsh functions by multiplying with Hadamard matrix. Essential component (others regarded noise) Hadamard Matrix H(3) Bit stream Spectral coeffs.

13. March 6, 200739th Southeastern Symposium on System Theory13 Generation of New Bit-Streams Perturbation Generation of new bit-stream by multiplying with Hadamard matrix Spectral components Essential component retained; noise components randomly perturbed New bit stream Bits changed Sign function -1 to 0

14. March 6, 200739th Southeastern Symposium on System Theory14 PARWAN Processor Reference: Z. Navabi, Analysis and Modeling of Digital Systems. New York: McGraw-Hill, 1993.

15. March 6, 200739th Southeastern Symposium on System Theory15 Power Spectrum for “Interrupt” Bit-Stream Spectral Coefficients Normalized Power Essential components Some noise components Random level (1/128) Analysis of 128 test vectors.

16. March 6, 200739th Southeastern Symposium on System Theory16 Power Spectrum for “DataIn[5]” Signal Theoretical random noise level (1/128) Normalized Power Spectral Coefficients Some essential components Some noise components Analysis of 128 test vectors.

17. March 6, 200739th Southeastern Symposium on System Theory17 RTL Design for Testability (DFT) Goals of DFT:  Improve fault coverage Most hard-to-detect transition faults were experimentally found to have poor observability XOR tree as DFT  Low area overhead  Low performance penalty  Hard-to-detect RTL faults used for observation test points  24 observation test points selected Hard-to-detect RTL transition faults To test output XOR tree

18. March 6, 200739th Southeastern Symposium on System Theory18 Experimental Results No of RTL Transition Faults No. of vectors CPU (s) RTL coverage (%) Gate-level fault coverage(%) 737160365277.07%47.84% RTL transition fault characterization PARWAN processor

19. March 6, 200739th Southeastern Symposium on System Theory19 Experimental Results ATPG used Version of PARWAN circuit CPU secs.* No. of vectors Stuck-at fault cov. (%) Transition fault cov. (%) RTL-spectral for transition faults Original6428670097.6081.85 DFT for t-f6428512098.2585.94 RTL-spectral combined stuck-at & transition tests Original902798.4781.85 DFT for s-a-f **708698.9185.87 DFT for t-f708698.7786.27 Gate-level FlexTest for transition faults Original43574131892.4473.79 DFT for t-f40119144496.2981.90 Random vectors Original5120082.2858.67 DFT for s-a-f **5120086.2065.82 * Sun Ultra 5, 256MB RAM ** N. Yogi and V. D. Agrawal, “Spectral RTL Test Generation for Microprocessors,” in Proc. 20th International Conf. VLSI Design, Jan. 2007, pp. 473-478.

20. March 6, 200739th Southeastern Symposium on System Theory20 Experimental Results Stuck-at Vectors

21. March 6, 200739th Southeastern Symposium on System Theory21 Experimental Results

22. March 6, 200739th Southeastern Symposium on System Theory22 Conclusion Spectral RTL ATPG technique applied to PARWAN processor for transition delay faults. Proposed ATPG method provides:  Good quality “almost” functional at-speed transition delay tests  Lower test generation complexity  Enables testability appraisal at RTL RTL based XOR tree as DFT improved fault coverage. Test optimization for multiple fault models:  Yogi and Agrawal, “Optimizing Tests for Multiple Fault Models,” submitted to the North Atlantic Test Workshop 2007.

23. March 6, 200739th Southeastern Symposium on System Theory23 Thank You ! Questions ?