1. CS402 PPP # 2 MIPS BASIC INFORMATION By George Koutsogiannakis 1

2. The MIPS microprocessor is developed by MIPS Technologies Inc. A company founded in 1984 by a group of researchers from Stanford University. http://www.mipstechnologies.com There are 2 basic architectures MIPS32 and MIPS 64 It is a RISC processor which stands for Reduced Instructions Set Computer. 2

3. MIPS can be little-endian or big-endian depending on the machine it is used. Little-endian means that the in a 4-byte word (32 bits) the Bytes are arranged as follows: Byte# Big-endian arrangement of bytes: Byte# 3 3 2 1 0 0 1 2 3

4. 4 When configured in big-endian order, byte 0 is always the least- significant (right-hand) byte. For example assume 4 words (32 bits each -4 bytes each). The arrangement in memory of the 16 bytes then is as follows: Bit # 8 781516 6 232431 0123 4 57 0 91011 12131415 Word address 0 4 8 12 Figure 1

5. 5 Questions: Which is the first word’s address (least significant word)? Why memory word address starts at 12? Exercise: Draw the same figure for little-endian order

6. 6 There are two MIPS architectures MIPS32 and MIPS64. We will concentrate on MIPS 32. Architecture refers to the instruction set, registers and other state, the exception model, memory management,virtual and physical address layout, and other features that all hardware executes (e.g. pipelining is an architecture issue) Implementation refers to the way in which specific processors apply the architecture (e.g. How caching works is an implementation issue). There is a main processor and two co-processors-each with their own set of registers

7. 7 Figure 2- MIPS 32 Memory Main processor Co-processor 1- FPU (Floating Point Arithmetic) Co-processor 2- Traps and Memory (sometimes referred as co-proces. 0) 32 Registers ALU Multiply Multiply Divide HILOW BadVAddrStatus Cause EPC 4 registers implemented by Spim. There are more registers PC

8. 8 PIPELINE A pipeline is divided into the following discrete parts, or stages : Fetch Arithmetic operation Memory access Write back As a result in the parallel pipeline implementation a number of instructions can be In the pipeline simultaneously.

9. 9 Cycle 3Cycle 2Cycle 1Cycle 4Cycle 5Cycle 6Cycle 7 FetchALU Memory WriteInstruction 1 Figure 3 Instruction 2 Instruction 3 Instruction 4

10. 10 Questions: How many instructions have finished execution in 7 clock cycles? What if we had super pipelining where each stage takes half a cycle? How many instructions are then finished in 7 cycles? What problems can pipeline present? See lab 2. Issue of delay.