1. IC-SOC Plan on Embedded Memory Defect Diagnostics and Yield Improvement Cheng-Wen Wu

2. mem4.11DTC, NTHU 2 Agenda (8:50-10:15)  Introduction  Cheng-Wen Wu—NTHU  Architecture & Compilation for Configurable Processors  Guoling Han/Jason Cong—UCLA  H.264 Advanced Video Codec Design  Youn-Long Lin—NTHU  Low-Power FPGA  Lei He—UCLA

3. mem4.11DTC, NTHU 3 Motivation & Purposes  Yield of on-chip memories dominates the overall chip yield  Effective memory diagnostics and failure analysis (FA) methodologies are necessary  We propose a systematic and automatic methodology for defect diagnostics  Fault pattern oriented approach  To effectively reduce candidate defects before physical FA

4. mem4.11DTC, NTHU 4 Fault Patterns  Combining failure patterns and fault types SAF0CFidSAF1 Failure Patterns Failure Patterns Fault Patterns Fault Patterns SAF 0 :00011000100 SAF 1 :00100001001 CFid 0 :00100110001 ……. Fault Types

5. mem4.11DTC, NTHU 5 Diagnostics Using Fault Patterns  A cause-effect approach: Fault Patterns Fault Patterns Defective Netlist Defective Netlist Realistic Fault Patterns Realistic Fault Patterns Prediction Stage Application Stage SimulationReduction Defect Dictionary Defect Dictionary Defect Candidates

6. mem4.11DTC, NTHU 6 Memory Defect Diagnostics (MDD) System Realistic Defect Injection Circuit-level Simulation Fault Pattern Generation Defect Dictionary Generation Faulty Circuits Simulation Results Fault Patterns Design Netlist Layout Defect Size Cond./Distr. Process In-Line Inspection March Dictionary Arch. RAM Spec. Scrambling Test Cond. Patterns Volt./Freq. Failure/Fault Pattern Analyzer AFA Fault Maps from MECA [12] Defect Dictionary Defect Candidates/Statistics

7. mem4.11DTC, NTHU 7 Fault Pattern Classification

8. mem4.11DTC, NTHU 8 CA Calculator Overview of FFA Short defect injection Layout Defect Distribution Layout Extractor Short Critical Area Calculator Open defect injection Open Critical area calculation Failure Factor Analyzer Defect Information Failure Factor

9. mem4.11DTC, NTHU 9 Defect Models ShortOpen Fault freeFaulty Fault freeFaulty Particle

10. mem4.11DTC, NTHU 10 Experiment on Industrial Designs Cell ACell B WL Gate Gnd Data Vdd BL Vdd BL Gnd Data % of Area = 114% # of Cont = 8.5 # of Via = 2 % of Area = 100% # of Cont = 8.5 # of Via = 3.5+1 Using 0.18μm CMOS Process Technology