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Micro Computers ClassYaron Sheffer, 1/99, p-1 Non Pipelined Read and Write Figure 6-7. Non-Pipelined Read and Write CLK ADDR ADS# NA# CACHE# W/R# BRDY#

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Presentation on theme: "Micro Computers ClassYaron Sheffer, 1/99, p-1 Non Pipelined Read and Write Figure 6-7. Non-Pipelined Read and Write CLK ADDR ADS# NA# CACHE# W/R# BRDY#"— Presentation transcript:

1 Micro Computers ClassYaron Sheffer, 1/99, p-1 Non Pipelined Read and Write Figure 6-7. Non-Pipelined Read and Write CLK ADDR ADS# NA# CACHE# W/R# BRDY# DATA DP PCHK# TO CPU VALID INVALID T1 T2 Ti T1 T2 Ti T1 TO CPU FROM CPU

2 Micro Computers ClassYaron Sheffer, 1/99, p-2 Non Pipelined Read and Write w/ Wait States CLK ADDR ADS# NA# CACHE# W/R# BRDY# DATA/DP PCHK# Figure 6-8. Non-Pipelined Read and Write with Wait States VALID FROM CPU TO CPU T1 T2 T2 Ti T1 T2 T2 T2 VALID

3 Micro Computers ClassYaron Sheffer, 1/99, p-3 Basic Burst Read Cycle CLK ADDR ADS# CACHE# W/R# KEN# BRDY# DATA/DP PCHK# Figure 6-9. Basic Burst Read Cycle TO CPU VALID T1 T2 T2 T2 T2 Ti

4 Micro Computers ClassYaron Sheffer, 1/99, p-4 Slow Burst Read Cycle CLK ADDR ADS# CACHE# W/R# KEN# BRDY# DATA/DP PCHK# Figure 6-10. Slow Burst Read Cycle TO CPU T1 T2 T2 T2 T2 T2 T2 T2

5 Micro Computers ClassYaron Sheffer, 1/99, p-5 Basic Burst Write Cycle CLK ADDR ADS# CACHE# W/R# BRDY# DATA/DP PCHK# Figure 6-11. Basic Burst Write Cycle T1 T2 T2 T2 T2 Ti VALID FROM CPU FROM CPU FROM CPU

6 Micro Computers ClassYaron Sheffer, 1/99, p-6 Inquire Cycle that Misses Cache CLK ADS# W/R# BRDY# DATA AHOLD EADS# ADDR AP INV HIT# HITM# APCHK# Figure 6-24. Inquire Cycle that Misses the Pentium ® Processor Cache FROM CPU FROM CPU TO CPU T1 T2 T2 Ti Ti T1 T2

7 Micro Computers ClassYaron Sheffer, 1/99, p-7 Inquire Cycle that Invalidates non-M-state Line CLK ADS# W/R# BRDY# DATA AHOLD EADS# ADDR/AP INV HIT# HITM# APCHK# Figure 6-25. Inquire Cycle that Invalidates a Non-M-State Line FROM CPU FROM CPU TO CPU T1 T2 T2 Ti Ti T1 T2

8 Micro Computers ClassYaron Sheffer, 1/99, p-8 Inquire Cycle that Invalidates M-state Line Figure 6-26. Inquire Cycle that Invalidates M-State Line CLK ADS# CACHE# W/R# BRDY# DATA AHOLD EADS# ADDR INV HIT# HITM# 1 2 3 4 5 6 7 8 9 10 11 T2 T2 Ti Ti T1 T2 T2 T2 T2 Ti Ti fr CPU to CPU fr CPU fr CPU fr CPU

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