1. Super Fast Camera System Performed by: Tokman Niv Levenbroun Guy Supervised by: Leonid Boudniak

2.  The concept: combine multiple “off the shelf” cameras, to create a sequence of frames to capture a fast moving object.  An FPGA will be used to coordinate and synchronize the cameras.  The image data will be read into a computer, where it will be processed. Project Overview

3.  Choose an appropriate image sensor, to fit our goals.  Design a system to handle data transfer from the cameras to the computer, and display it as a movie. Project Goals

4. Choosing The Sensor Several image sensors were examined and two were found appropriate for the problems at hand. It has become apparent that building the printed circuit board (PCB) is time consuming and beyond the scope of this project. To overcome this obstacle we chose a PCB camera from photon-focus -OEM-D640C-66 Problem: the PCB at hand doesn’t have a separate readout control.

5.  The photon focus module as well as most image sensors/Camera modules operate at 33MHz~66MHz Pixel rate  We planed to operate the module at 33 MHz pixel rate, 8 bit per pixel => 33 Mbyte/sec  In case of N cameras sending data in parallel, effective input data rate to the system is 33*N Mbyte/sec. N=2 => 66 Mbyte/sec=528 Mbps  Note: This is peak rate, average rate is lower due to line pause.  Conclusion: can’t transfer the data directly to the PC. (no existing connection is fast enough). System Data Rates

6. Basic Block Diagram

7. General Approach As dictated by data rate, we divided the data traffic into two separate parts. –Transferring data from the cameras to an on- chip memory (SDRAM). This is the crucial point of the system, since it must operate in real time. –Transferring the images from the DRAM to the PC.

8. Transferring To Memory No stand alone SDRAM controller exists in the lab. Implementing one is complicated and time consuming. Other solutions : –Using the existing SDRAM controller’s interface to the PLB, for fast read using DMA. Never been attempted in the lab. –Using the PowerPC for reading from the camera and writing to the DRAM. Slower but simple.

9. Transferring To Memory cont’ DMA was tested without results: –Design using IPIF interface remained inactive. –Example design provided by Xilinx® yielded similar behavior. Usage of PowerPC: –With our peripheral designed as PLB slave, data was transferred successfully to the SDRAM.

10. Transferring To PC Since there were no time constrains we used the simplest way of using the RS-232 for transferring the data to the PC. The data was received by hyper terminal. The file is than processed by a MATLAB program to yield a sequential movie.

11. Example Of System Operation A command signal indicates start of integration Cameras send picture pixel by pixel. 4 pixels are packed together and indexed. A read/write operation stores the packet in the SDRAM. Once all the pixels were stored, the data is transferred to the PC via the RS-232

12. Results And Analysis Testing shows successful transfer of 4 bytes in 14 bus cycles: This is almost half of the desired bandwidth.

13. Improvement iteration Assembly code Compiled code is not optimized. Assembly enables: loop unrolling, more efficient memory transaction order (LD after LD instead of SW after LD). Buffering Software controlled access are of single word only. We tried to use cache commands to initiate burst transaction. Double word Use of 64bits data structure to force use of full PLB bus width (64 bits)

14. Conclusion Of all methods, only DMA is theoretically able to support the desired input rate. Software transaction are inefficient. Design is still limited to small number of cameras. Usage of cameras with readout control will enable lossless data transfer.

15. Future Development Memory tapping The lab has a design that allows to tap the memory controller directly, avoiding the IPIF. Design is incomplete, needs adaptation to our design, but might improve access: –No IPIF overhead –No bus contention –Burst operations

16. Future Development cont’ Bus clock acceleration –Presently bus operates with a 100 MHz clock. –Providing faster bus clock theoreticaly improves rates. Disadvantages –SDRAM might not support such frequencies. –Unpredicted behavior due to cross capacitances and inductance in high frequencies.

17. Added Value Knowledge of major imaging sensor technologies in the world today. Project scheduling & challenges. System design principles. Embedded CPU system. VHDL language basics and writing style. FPGA concepts.

18. Thank you We’d like to thank the laboratory staff: Kostia, Ilan, Ina and Eli for their support, good advices and kind words in times of need. Special thanks goes to Leonid, who was available at all times and sharing his productive insights.

19. Backup Foils

20. System Design Bus interface Main FIFO Camera data converter & FIFO Camera FIFO arbiter Controller Camera simulation