1. CS150 Newton5.2.1 Outline mLast time: ÜImplementation of logic functions: TTL, CMOS ÜDelay models: Transition time, propagation delay ÜHazards and "Glitches" ÜHazard-free design ÜSummary of combinational circuit design mThis lecture: ÜSwitch-level implementation ÜDesign Using Multiplexers ÜShannon Expansion ÜBinary Decision Diagrams (BDDs)

2. CS150 Newton5.2.2 Implementation of Logic Using Switches AB C NMOS A B C CMOS AB C Switch, Relay AB A B XY X Y AB C

3. CS150 Newton5.2.3 Series-Parallel Networks

4. CS150 Newton5.2.4 Multiplexer Trees Using Switches Z A B B C C C C

5. CS150 Newton5.2.5 Multiplexer  multiplexer EN SEL     b b b b D0 D1 D2 Dn-1  b Y s select enable n = 2^s data sources data output Consider b=1, s=1 Consider b=1, s=2

6. CS150 Newton5.2.6 Design Using Multiplexers Z = AB + C 0 1 2 3 4 5 6 7 Z ABC S0S0 S1S1 S2S2

7. CS150 Newton5.2.7 Design Using Multiplexers Z = ABD + C + BD 0 1 2 3 4 5 6 7 Z S0S0 S1S1 S2S2

8. CS150 Newton5.2.8 Binary Decision Diagrams 0 0 X1 X2 X3 1 1 0 0 1 1 f = X1.X2 + X3 m In general: fv = Xv' flow + Xv fhigh low child high child 0 0 X3 1 1 1 1 1 1 012 3 456 7

9. CS150 Newton5.2.9 Implementation of Logic Using Switches Shannon Expansion: (T15)F(X,Y,Z) = XF(1,Y,Z) + X'F(0,Y,Z) (T15')F(X,Y,Z) = (X+F(0,Y,Z))(X'+F(1,Y,Z))

10. CS150 Newton5.2.10 Binary Decision Diagrams 0 0 X1 X2 X3 1 1 0 0 1 1 1 1 f = X1.X2 + X3 f1 = 1 f2 = X3 f3 = X2 ' X3 + X2 low child high child V1 V2 V3

11. CS150 Newton5.2.11 Use of BDDs for Verification 0 0 X1 X2 X3 1 1 0 0 1 1 1 1 m Condition on edges forces order on variables. m Order must be consistent with all edges. m For each edge, parent before child in the order. ÜX1 X2 X3

12. CS150 Newton5.2.12 Use of BDDs for Verification 0 0 X1 X2 X3 1 1 0 0 1 1 1 1 V1 V2 V3 m V1 is a redundant vertex m V2, V3 represent the same function m A BDD is a reduced binary decision graph Ü Reduction is O(N*log(N)) for N verticies

13. CS150 Newton5.2.13 Use of BDDs for Verification X1 X3 X2 0 0 1 1 m Each vertex corresponds to a partial assignment of inputs. Ü V1: 0-, 10 m Result of reduction is a canonical form. V1

14. CS150 Newton5.2.14 Combinational Verification Using Canonical Form Convert to BDD Convert to BDD Isomorphism Check Behavior Functions the system must implement Implementation-independent description Behavior Functions the system must implement Implementation-independent description Register Components and their interconnections Std. components & ROM, ASIC, PLD Register Components and their interconnections Std. components & ROM, ASIC, PLD Gate Low-level components & nets In terms of ASIC library Gate Low-level components & nets In terms of ASIC library Electrical Voltages, currents and detailed models Electrical Voltages, currents and detailed models Switch Transistor-level description Logic Values and Strengths Switch Transistor-level description Logic Values and Strengths

15. CS150 Newton5.2.15 Connectivity Verification Network 1 Network 2 Hash Table compute signature compute signature

16. CS150 Newton5.2.16 Connectivity Verification (1)  Read Network1 and Network2 into separate graph data structures (usually, node = transistor or gate, edge = connection). (2)  Compute signatures for nodes or edges or both.  Type-specific: Gate type, #inputs, #outputs  Network-specific (local): Fanin types, #fanouts, fanout types  Network-specific (global): Distance from primary inputs, primary outputs, nodes that are known to be the same in each network (e.g. named, primary inputs or outputs ("seeds")). (3) Hash signatures from both networks into single hash table. (4)  If a hash table cell has:  > 2 nodes: ignore for now  = 2 nodes: a match has been found  = 1 node: an (easy!) error has been found (5) Add links between networks for nodes that have been matched. (6) Recompute hash functions for un-bound nodes and repeat until done or no change.