1. Camera Auto Focus Presentation 4, February 14 th, 2007 Team W1: Tom Goff (W11) David Hwang (W12) Kate Killfoile (W13) Greg Look (W14) Design Manager: Bowei Gai Project Goal: Design a low-power, small auto focus chip for a camera or other hand-held device

2. Status Last Time –C implementation –Attempt at floor plan This Week Structural Verilog completed Major architecture revision Revised floor plan In Process… Power control logic implementation Low-power component selection Unfinished Schematic Layout Extraction, LVS, post-layout simulation

3. Big Picture Recap

4. Design Decisions Optimization of rules Reduction of registers, additional preprocessing unit Led to a huge change in architecture

5. Remember this?

6. New Architecture

7. AG Preprocessor Zoom Out

8. Delta I Preprocessor Zoom Out

9. Rule Logic Zoom Out

10. Transistor Count ComponentFull Chip Count Registers1,600 Comparators2,100 FP multiplier3,000 FP adder2,000 Subtractors2,000 Int to float logic1,040 Power control2,000 Buffers2,000 Muxes2,480 Total~18,220 Optimizes down from 25,230!

11. Floor Plan Dimensions: 238 x 266 Let’s make sense of all the wires and modules here…

12. 3 Input Multiply Input: 10 bit values (3) Output: 10 bit value Accumulator Input: 10 bit multiply value 10 bit register value Output: 10 bit acc. value AG Preprocessor Input: 8 bit AG value Output: 8 bit rule values (3) Input Register Input: 10 bit Delta I Output: 9 bit Delta I Delta I Preprocessor Input: 9 bit Delta I Output: 2 bit range 9 bit subtract result (2) Input Register 8 bit AG Int to Float Input: 8 bit rule values (3) Output: 10 bit rule values (3) Power Logic Input: 1 bit ready signal Output: Control lines to registers and muxes

13. Floor Plan ComponentSize ( µm² x µm²) Size (µm²) Registers52 x 84,847 Comparators54 x 134,233 FP multiplier115 x 10011,494 10 bit muxes54 x 146,080 FP adder143 x 649,161 Subtractors54 x 452,425 Int to float logic42 x 222,766 Power control88 x 837,252 8 bit muxes43 x 132,865 Total~63,000

14. Testing of Components

15. Structural Verilog Complete structural wiring Writing an exhaustive testbench

16. Power Logic Registers used to shut down modules not in use Controls 3-input multiplier args Controls accumulator and output registers

17. Next Steps Produce module schematics Continue optimizing logic Implement power logic control

18. Work Distribution Tom: Verilog implementation Dave: Verilog implementation Greg: Gate level multiplier, adder Kate: Floor plan Bowei: Destructive criticism

19. Problems Looking into power gating Group members can only work for 10 hours straight before going insane or feral or both

20. Questions

21. References None for this week