1. Final Presentation: April 25 th, 2005 Seri Abd Rauf Fatima Boujarwah Juan Chen Liyana Sharipp Arti Thumar 18-525: Integrated Circuit Design Project, Spring 2005 Project Manager: Bobby Colyer Overall Design Goal: Implementing Noise Canceling Algorithm in Hardware

2. 18-525: Integrated Circuit Design Project, Spring 2005 Got an iPod? Can you hear the noise? Want to know why? Cell phone? Car? PDA? No?

3. Most devices that we use throughout the day have a noise canceling component –Audio –Visual –Motion 18-525: Integrated Circuit Design Project, Spring 2005

4. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layout 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

5. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

6. Also known as the Intelligent Microsurgical Instrument Project A research done here at CMU, led by Prof Riviere and Dean Khosla Project Goal: To enhance accuracy in microsurgery Problem Definition: Physiological Tremor Non-tremulous errors Method Weighted Fourier Linear Combiner (WFLC) for noise canceling purposes How does this help solve the problems?

7. WFLC Revised Flow ChartOriginal Flow Chart 18-525: Integrated Circuit Design Project, Spring 2005

8. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

9. Microsurgical InstrumentsHuman-Computer Interfaces Vehicle ManeuveringHearing Aid

10. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

11. Goal: To minimize noise Algorithm: Based on adaptive filtering depending on signal weights Pseudo-code: i)Take the input signal and model it using Fourier Transform ii)For each sample, model it by approximating the weight constant and feeding it back to the next sample iii)Each sample model is then subtracted from the original input signal to monitor the error

12. Output w1 + - Sin(sumw0) Integration Block Integrator Block Cos(sumw0)w2 Input LMS w0 Error Generate Adaptive Weights to Calculate Output Take Fourier Transform of Input Signal using previous Error Sample Output Subtracted from Input Signal to Generate Current Error Repeat the Process for the next Sample Input

13. counter ROM Sine Converter Cosine Converter 0 1 0 1 FPMult 1 FPMult 2 0 1 0 1 0 1 FPAdd FPAdd/Sub Datum Offset w1 Out FPSub e AddOne w2 mu FPMult 3 18-525: Integrated Circuit Design Project, Spring 2005

14. The BIG Picture Marketing Potential Behavioral/ Algorithm Description Design Process Floorplan Evolution Layouts Verification Challenges Chip Specifications Finale 18-525: Integrated Circuit Design Project, Spring 2005

15. Floating Point Multipliers Array vs Wallace tree structures for power saving 18-525: Integrated Circuit Design Project, Spring 2005

16. Wallace + Booth vs Wallace for better layout design –saved 2K transistors –inserted smaller modules in top level to fill up the white space Buffered each bit of the output 18-525: Integrated Circuit Design Project, Spring 2005

17. Floating Point Adders Ripple Carry Adder vs. Carry Look-ahead Adder Mirror Adder vs. Mux-based Adder Mirror AdderMux-based Adder # of transistors2418 Area11.52 x 5.415.16 x 5.62 Output signalStableUnstable 18-525: Integrated Circuit Design Project, Spring 2005

18. Changed the general FPAdd/Sub (with input signal ‘sub’) for all the three adders to: –FPAdd for the top adder –FPSub for the middle adder –FPAddSub for the bottom adder Barrel shifter vs. Logarithmic shifter –Barrel shifter is used during normalizing – consumes less power –Log shifter is used during denormalizing – easier to extract the sticky bits Changed Ripple Borrow Subtractor to Ripple Carry Adder with Carry In = 1 Eliminate ‘sub’ and minimize the logic for sign bit 18-525: Integrated Circuit Design Project, Spring 2005

19. MUX and Register Designed MUXes based on where the inputs and outputs are in the top level floorplan Designed registers based on their functionalities and inputs/outputs positions –Mu, Offset, Datum: Negative Edge Triggered DFF –w1, w2, Out, e : Clear-Alternate Enabled DFF 18-525: Integrated Circuit Design Project, Spring 2005

20. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

21. 5 Floating Point Adders?

22. 18-525: Integrated Circuit Design Project, Spring 2005 Need better routing channels Need to redesign muxes to avoid congestions Move this there…

23. 18-525: Integrated Circuit Design Project, Spring 2005 And we thought this would be our final floorplan…

24. 18-525: Integrated Circuit Design Project, Spring 2005 The multipliers turned out to be smaller!

25. 18-525: Integrated Circuit Design Project, Spring 2005

26. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

27. Denormalizing Normalizing Output Logic Add/Sub

28. 18-525: Integrated Circuit Design Project, Spring 2005

29. Rounding Unit Wallace Tree Multiplier

30. 18-525: Integrated Circuit Design Project, Spring 2005

31. Alternator Buffers 18-525: Integrated Circuit Design Project, Spring 2005

39. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

40. *Test Files are from Robot Assisted Needle Insertion Research Conducted by Professor Cameron Riviere These inputs approximate to: Constants: MU = 0.1 OFFSET = 10 Inputs: DATUM = 10.34058900 10.42289600 10.49148600 10.59208400 10.67439200 10.72926400 10.77041800 10.78870800 10.74755400 18-525: Integrated Circuit Design Project, Spring 2005

41. Behavioral resultsStructural results Output Error Similar Plots: Slight Differences due to 16-bit Floating Point Units. 18-525: Integrated Circuit Design Project, Spring 2005

42. **First three test vectors verify correctness of the layout Output Bits 0-7: 01110111 Clean Output Signals: 1.8V 18-525: Integrated Circuit Design Project, Spring 2005

43. The BIG Picture Marketing Potential Behavioral/ Algorithm Description Design Process Floorplan Evolution Layouts Verification Challenges Chip Specifications Finale 18-525: Integrated Circuit Design Project, Spring 2005

44. Transistor Count –Solution: Reused hardware Hardware Sharing –Caused timing issue –Split the circuit into two cycles Sufficient Signal Strength –Improved Vdd and Gnd rail connections –Buffering techniques

45. The BIG Picture Marketing Potential Behavioral/ Algorithm Description Design Process Floorplan Evolution Layouts Verification Challenges Chip Specifications Finale 18-525: Integrated Circuit Design Project, Spring 2005

46. Size of Design364.275µm x 300.96µm Aspect Ratio1:1.21 Transistor Count25385 Density0.232 transistors/µ 2 Clock Frequency50KHz Power2.507mW Pin Count84 pins 18-525: Integrated Circuit Design Project, Spring 2005

47. Vdd! Gnd! In/Out Datum Mu Offset Clk Reset In Out e Out Total # of Pins: 84 18-525: Integrated Circuit Design Project, Spring 2005

48. 1.The BIG Picture 2.Marketing Potential 3.Behavioral/ Algorithm Description 4.Design Process 5.Floorplan Evolution 6.Layouts 7.Verification 8.Challenges 9.Chip Specifications 10.Finale 18-525: Integrated Circuit Design Project, Spring 2005

49. We will never be the same… Everyone must have a cell phone with a good noise canceling function Shopping is not a priority anymore. Metal 3 is not ‘in’ this season The early bird gets the worm…but can we get up? (hmmm, did we ever get to sleep? The Butterfly effect applies to EVERYTHING, including…floorplannig

50. 18-525: Integrated Circuit Design Project, Spring 2005

51. There are hundreds of applications for noise cancellation devices in our everyday lives Such algorithms are crucial in improving the quality of lives of many people 18-525: Integrated Circuit Design Project, Spring 2005 So, in conclusion, our chip:  Is universally effective and efficient in canceling noise  Can be used to cancel all types of noise  Will save lives

52. http://www-2.cs.cmu.edu/~micron/index.htm http://www-2.cs.cmu.edu/~camr/research.html http://www.ri.cmu.edu/projects/project_32.html http://www.eecs.berkeley.edu/~mounir/ee241/ee241.part2.pdf http://www.ece.cmu.edu/~lowpower/cicc96.pdf http://www.eecs.berkeley.edu/~mounir/ee241/ee241_final_report.pdf C. N. Riviere, “Predicting Respiratory Motion for Active Canceling During Percutaneous Needle Insertion”, Oct. 2001 http://www.whynot.net/view_idea.php?id=1579 www.owlnet.rice.edu/~elec301/Projects00/site/design.html 18-525: Integrated Circuit Design Project, Spring 2005