1. Performance Analysis of Two Synchronizers Zhen ZhangJim Garside APT group, School of Computer Science University of Manchester

2. 2/16 Necessities for Data Synchronization Multi-Clock Domains in SoC Devices –Difficulties in Single Clock Distribution –Modules with Different Frequencies –Dynamical Changing Clock Relationships –GALS architecture

3. 3/16 Choice of Synchronizers Mutual Relationships of Clock Domains –Most General Case: Mutually Asynchronous Reliability and Performance of Synchronizers –Metastability –Latency and Throughput Systematic Analysis of Two-Flop Synchronizer Families

4. 4/16 Two-Flop Synchronizer

5. 5/16 Time Boundaries for Forward Cycle

6. 6/16 Plot of Time Boundaries

7. 7/16 Probability and Average Forward Cycle

8. 8/16 Average Forward Cycle

9. 9/16 Fast Four-Phase Synchronizer* *“Zero latency synchronizers using four and two phase protocols”, R.Dobkin and R.Ginosar, Technical Report, Oct 2007

10. 10/16 Time Boundaries

11. 11/16 Plot of Forward and Backward Cycle Time Boundaries

12. 12/16 Average Forward and Backward Cycles

13. 13/16 Conclusion Performance analyses of two recognized synchronizers are developed Analytical models for average data cycles provide designers with more accurate information for performance comparison purpose Non-linear behaviour of backward cycle indicates the dependencies on forward cycle Full analysis of two-phase synchronizer is conducted (not shown in this presentation)

14. 14/16 Future Work Analyze forward and backward cycle interactions for two-flop and four-phase synchronizers Expand the analysis of single word transfer to burst-mode transfer Incorporate effects of metastability and interconnection delays into our model Apply similar analysis to other synchronizers

15. 15/16 Questions