1. Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control Puneet Gupta 1 Andrew B. Kahng 1 Puneet Sharma 1 Dennis Sylvester 2 1 ECE Department, University of California – San Diego 2 EECS Department, University of Michigan, Ann Arbor http://vlsicad.ucsd.edu http://vlsida.eecs.umich.edu

2. Outline Introduction Introduction L Gate biasing methodology L Gate biasing methodology Experiments and results Experiments and results Process effects Process effects Summary Summary

3. Introduction Leakage significant portion of total power Leakage significant portion of total power High leakage  short battery life High leakage  short battery life V T increase  Leakage power reduction V T increase  Leakage power reduction Most common technique: Multiple doping profiles Most common technique: Multiple doping profiles Our work: increase L Gate to increase V T Our work: increase L Gate to increase V T No additional process steps No additional process steps Leakage variability Leakage variability 0.9 1.0 1.1 1.2 1.3 1.4 05 10 1520 Normalized Leakage (Isb) Normalized Frequency 20x 30%

4. Key Idea Variation of leakage and delay (each normalized to 1) for an NMOS device in an industrial 130nm technology  Slightly increase (bias) the L Gate of devices Impact on Leakage and Delay No circuit performance loss if only non-critical devices are biased Nominal L Gate Impact on LeakageVariability Biasing

5. Outline  Introduction L Gate biasing methodology L Gate biasing methodology Experiments and results Experiments and results Process effects Process effects Summary Summary

6. Methodology Extend a standard cell library with biased L Gate versions of all cells Extend a standard cell library with biased L Gate versions of all cells Optimize circuit for leakage by using biased L Gate versions for non-critical cells Optimize circuit for leakage by using biased L Gate versions for non-critical cells How much to bias by? How much to bias by? Small bias Small bias Small leakage reduction beyond 10% biasing Small leakage reduction beyond 10% biasing Preserve pin-compatibility  Technique can be applied post- routing Preserve pin-compatibility  Technique can be applied post- routing Bound cell delay penalty, minimize leakage Bound cell delay penalty, minimize leakage

7. L Gate Biasing Granularity Given a cell delay penalty, what should the biasing for each device in it be? Given a cell delay penalty, what should the biasing for each device in it be? Three levels of granularity Three levels of granularity Technology-level Technology-level All devices in all cells have same biased L Gate All devices in all cells have same biased L Gate Cell-level Cell-level All devices in a given cell type have same biased L Gate All devices in a given cell type have same biased L Gate 135nm 137nm NAND2 Device-level Device-level All devices free to have independently biased L Gate All devices free to have independently biased L Gate Simplification: In each cell, NMOS devices have one gate length and PMOS devices have another

8. Outline  Introduction  L Gate biasing methodology Experiments and results Experiments and results Process effects Process effects Summary Summary

9. Validation Flow Library characterization Library characterization 8 cells, 4 variants of each cell 8 cells, 4 variants of each cell Hspice (using autochar) Hspice (using autochar) Dual L Gate circuit optimization Dual L Gate circuit optimization DUET/TILOS like DUET/TILOS like Pick cells on non-critical paths, replace with biased variants Pick cells on non-critical paths, replace with biased variants Cells with higher leakage reduction and higher slack are replaced first Cells with higher leakage reduction and higher slack are replaced first Test cases: ISCAS ’ 85 combinational + alu128 Test cases: ISCAS ’ 85 combinational + alu128 Autochar Hspice Spicemodels Low V T, Nominal L Gate Low V T, Biased L Gate Nominal V T, Nominal L Gate Nominal V T, Biased L Gate Generated Library Circuit Optimizer Synthesized Circuit Netlist Optimized

10. Leakage Savings 8.00% 3.40% 15.35% 10.89% 21.1% 12.40% 24.80%24.70%

11. Outline  Introduction  L Gate biasing methodology  Experiments and results Process effects Process effects Summary Summary

12. Manufacturability Biasing of the order of CD tolerance  printability questionable Biasing of the order of CD tolerance  printability questionable OPC: Mentor Calibre with CD tolerance of 2nm, lithosimulation using printimage OPC: Mentor Calibre with CD tolerance of 2nm, lithosimulation using printimage Device Number Gate Length (nm) PMOSNMOS UnbiasedBiasedDiff.UnbiasedBiasedDiff. 1125132+7126132+6 2124126+2126129+3 3124126+2126129+3 4121127+6124130+6 5121127+6122128+6 6122128+6122128+6 7125131+6124131+7 Printed dimensions of unbiased and biased device versions of AND2X6 Nominal L Gate = 130nm, Biased L Gate = 136nm High correlation between drawn and printed L Gate High correlation between drawn and printed L Gate

13. Leakage Variability Leakage variability estimated with 2000 Monte-Carlo simulations on alu128  WID =  DTD = 3.3nm (L Gate variations assumed to be Gaussian w/ zero correlation) 40-55%reduction in spread

14. Outline  Introduction  L Gate biasing methodology  Experiments and results  Process effects Summary Summary

15. Summary Conclusions Conclusions L Gate biasing gives fine control over the delay-leakage tradeoff L Gate biasing gives fine control over the delay-leakage tradeoff L Gate biasing reduces leakage in SVT and DVT designs L Gate biasing reduces leakage in SVT and DVT designs The approach does not increase process cost, is easy to incorporate in existing design flows The approach does not increase process cost, is easy to incorporate in existing design flows Ongoing work Ongoing work Improved biasing-based leakage optimization heuristics Improved biasing-based leakage optimization heuristics Gate length selection at true device-level granularity Gate length selection at true device-level granularity Evaluation of gate length biasing at future technology nodes Evaluation of gate length biasing at future technology nodes Using asymmetry of timing slacks, rise and fall transitions to optimize power with L Gate biasing Using asymmetry of timing slacks, rise and fall transitions to optimize power with L Gate biasing

16. Thank You!