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ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering
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How are Gates Implemented? By Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) PMOS if source/drain are p-type semiconductor NMOS if source/drain are n-type semiconductor CMOS (complementary MOS) GATE SOURCEDRAIN Oxide 5 nm Gate length 20 nm Hair=0.1mm 1000um=1mm 1000nm=1um
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NMOS and PMOS
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CMOS NOT gate
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CMOS NAND Gate Pull up: Pull down:
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CMOS NOR Gate Pull up: Pull down:
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Example: Logic Realization Realize the following logic: Pull up Pull down:
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Negative Logic
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NMOS Gates
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NOT Gate
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NAND and NOR Gates
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Fan-in Fan-out and Buffers
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High Fan in Fan-in: Number of inputs Fan-out = Number of outputs This gate has large fan in Large delay
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High Fan out: Large switching time
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Buffer Each buffer can drive an output. Just two inverters in series.
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Tri-State Buffer
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Transmission Gate
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Example XOR
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