1. Embedded Systems Interrupts C.-Z. Yang http://syslab.cse.yzu.edu.tw/~czyang Sept.-Dec. 2001

2. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts2 Context Awareness Since embedded systems are closely relevant to the contexts, how can these external events be noticed?

3. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts3 I/O Interrupts The most common approach is to use interrupts. –Interrupts cause the microprocessor in the embedded system –to suspend doing whatever it is doing and –to execute some different code instead. Interrupts can solve the response problem, but not without some difficult programming, and without introducing some new problems of their own.

4. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts4 I/O Interrupts The flow –Step 1: Interrupts start with a signal from the hardware. –Step 2: The signal notifies the CPU to react the event.

5. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts5 Interrupt Service Routines The main job is to react the interrupts. Typically, interrupt service routines also must do some miscellaneous housekeeping chores, –Reset the interrupt-detecting hardware –Enable processing interrupts of lower priorities

6. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts6 ISR vs. Procedure Calls To execute ISRs, there is NO CALL instruction. –The microprocessor does the call automatically. An array, interrupt vector, of addresses is used to point to appropriate ISRs. –ISRs must be loaded when the computer is turned on. Interrupts can be masked. The context need to be saved.

7. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts7 Two Basic Models Synchronous –Returning the control of CPU to the user process must be after the completion of the ISR. Asynchronous – The control is returned without waiting for the I/O to complete.

8. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts8 Some Common Questions How does the microprocessor know where to find the interrupt routine when the interrupt occurs? How do microprocessors that use an interrupt vector table know where the table is? Can a microprocessor be interrupted in middle of an instruction?

9. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts9 Some Common Questions If two interrupts happen at the same time, which interrupt routine does the microprocessor do first? Can an interrupt request signal interrupt anther interrupt routine? What happens if an interrupt is signaled while the interrupts are disabled?

10. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts10 Some Common Questions What happened if I disable interrupts and then forget to re-enable them? Can I write my interrupt routines in C?

11. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts11 The Shared-Data Problem

12. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts12 A Powerful ISR Design Can the ISR do everything you want? –Yes, but this is very impractical. main() { int i; // setting up ISRs // do nothing but an empty loop while(1) i=i+0; } SampleISR() { newVal:= ReadADConverter() call StartNewConversion() … } SampleISR() { newVal:= ReadADConverter() call StartNewConversion() … }

13. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts13 A Practical Approach The ISR should do the necessary tasks –moving data from I/O devices to the memory buffer or vice versa –handling emergent signals –signaling the task subroutine code or the kernel The ISR needs to notify some other procedure to do follow-up processing. Task Code ISR Shared Variables

14. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts14 Accessing the Shared Data However, this may cause the shared data problem. ISR Task Code Interrupt

15. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts15 The Shared Data Problem The unexpected interrupt –may cause two readings to be different, –even though the two measured temperatures were always the same. What can we improve this? –Testing these temperature measurements directly!

16. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts16 Directly Testing The new code ISR Task Code Testing

17. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts17 A Bug Harder to Be Detected The compiler translation Interruptible

18. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts18 Characteristics of the Shared-Data Bug A bug that is very hard to find. –It does not happen every time the code runs. –The program may run correctly in most time. –However, a false alarm may be set off sometimes. How can you trace back if the embedded system has already exploded?

19. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts19 Solving the Shared-Data Problem

20. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts20 The Simplest Solution Just disable interrupts when the shared data are used by the task code.

21. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts21 The Assembly Code Disabling Interrupts

22. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts22 Atomic Instructions/Sections A More Convenient Way –Use some atomic instructions supported by the hardware. An instruction is atomic if it cannot be interrupted. The collection of lines can be atomic by adding an interrupt-disable instruction. A set of instruction that must be atomic for the system to work properly is often called a critical section.

23. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts23 Another Example A buggy program –imprecise answer Interrupt

24. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts24 Several Possible Solutions Disable the interrupt A buggy solution - Interrupts will not be appropriately enabled. A buggy solution - Interrupts will not be appropriately enabled.

25. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts25 A Better Code Changing the timing of return()

26. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts26 The Best Way The nested interrupts

27. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts27 Another Potential Solutions Doing things in the ISR

28. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts28 Potential Bugs If the microprocessor’s registers are large enough to hold a long integer, then the ASM code is atomic. However, if the registers are too small to hold a long integer, the the ASM will have the same problem.

29. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts29 A volatile Case Where is the variables?

30. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts30 A volatile Case The volatile keyword allows you to warn the compiler that certain variables may change because of interrupt routines. If this keyword is not supported, you can still get the similar result by turning off the compiler optimizations.

31. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts31 Interrupt Latency

32. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts32 One Obvious Question How fast does my system respond to each interrupt? –The longest period of time during which that interrupt is disabled. –The period of time it takes to execute any ISR for interrupts that are of higher priority than one in question. –How long it takes the microprocessor to stop what it is doing, do the necessary bookkeeping, and start executing instructions within ISR. –How long it takes the ISR to save the context and then do enough work that what it has accomplished counts as a “response”.

33. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts33 Next Question How do I get the times associated with the four factors? –Factor 3 from the data book –Factor 1, 2, and 4 through a benchmark program count the machine cycles

34. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts34 So, Make Your ISR Short The four factors control interrupt latency and, therefore, response. Although lower-priority interrupts are presumably lower priority because their response time requirements are less critical, this is not necessarily license to make their response dreadful.

35. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts35 Disabling Interrupts The remaining factor that contributes to interrupt latency is the practice of disabling interrupts. However, this needs to be carefully designed to meet the deadline requirements.

36. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts36 An Example Worst case latency

37. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts37 If Design Requirement is Changed Low-end processor Network enhancement

38. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts38 Alternatives to Disabling Interrupts Two variable sets

39. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts39 Two Variable Sets This simple mechanism solves the shared- data problem, because the ISR will never write into the set of temperatures that the task code is reading. However, the while-loop may be executed twice before it sets off the alarm.

40. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts40 A Queue Approach The shared-data problem is also eliminated.

41. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts41 A Queue Approach main()

42. 元智大學資訊工程系 czyang@acm.orgEmbedded Systems - Interrupts42 A Queue Approach However, this code is very fragile. Either of these seemingly minor changes can cause bugs.