1. Sequential Multiplication Lecture L6.4

2. Multiplication 13 x11 13 143 = 8Fh 1101 x1011 1101 100111 0000 100111 1101 10001111

3. Multiplication 1101 x1011 1101 100111 0000 100111 1101 10001111 1101 00001011 01101101 adsh 1101 10011110 adsh 1001111 sh 1101 10001111 adsh

4. Sequential Multiplier Use BTN4 to load SW into Ra and Rb and then display product in Rp Control signals: aload bload pload dmsel m2sel(1:0) mult_start mult_done

5. Three consecutive pushings of BTN4 Start multiplication Wait for mult_done Control signals: aload bload pload dmsel m2sel(1:0) mult_start mult_done

6. VHDL Canonical Sequential Network State Register Combinational Network x(t) s(t+1) s(t) z(t) clk init present state present input next state present output process(clk, init) process(present_state, x)

7. -- Title: Mult Control Unit library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity mult_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; BTN4, mult_done: in STD_LOGIC; m2sel: out STD_LOGIC_VECTOR (1 downto 0); aload, bload, dmsel, mult_start: out STD_LOGIC; pload: out STD_LOGIC ); end mult_control;

8. architecture mult_control_arch of mult_control is type state_type is (sA, sB, sC, sD, sE, sF, sG, sH); signal current_state, next_state: state_type; begin C1: process(current_state, BTN4, mult_done) begin -- Initialize all outputs pload <= '0'; dmsel <= '0'; aload <= '0'; bload <= '0'; m2sel <= "00"; mult_start <= '0'; mult_control.vhd

9. case current_state is when sA =>--wait for BTN4 up if BTN4 = '1' then next_state <= sA; m2sel <= "11"; else next_state <= sB; end if; when sB =>--wait for BTN4 down if BTN4 = '1' then next_state <= sC; aload <= '1'; -- A <- SW m2sel <= "00"; else next_state <= sB; m2sel <= "11"; end if;

10. when sC =>--wait for BTN4 up if BTN4 = '1' then next_state <= sC; m2sel <= "00"; else next_state <= sD; end if; when sD =>--wait for BTN4 down if BTN4 = '1' then next_state <= sE; dmsel <= '1'; bload <= '1'; -- B <- SW m2sel <= "01"; else next_state <= sD; m2sel <= "00"; end if;

11. when sE =>--wait for BTN4 up if BTN4 = '1' then next_state <= sE; m2sel <= "01"; else next_state <= sF; end if; when sF =>--wait for BTN4 down if BTN4 = '1' then next_state <= sG; pload <= '1'; m2sel <= "11"; mult_start <= '1'; else next_state <= sF; m2sel <= "01"; end if;

12. when sG => --mult_start <= '1' next_state <= sH; mult_start <= '1'; when sH => --wait for mult result if mult_done = '0' then next_state <= sH; pload <= '1'; m2sel <= "11"; else next_state <= sA; m2sel <= "01"; end if; end case; end process C1;

13. statereg: process(clk, clr)-- the state register begin if clr = '1' then current_state <= sA; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process statereg; end mult_control_arch;

14. mpp 1101 00001011 01101101 adsh 1101 10011110 adsh 1001111 sh 1101 10001111 adsh a = c:b = mpp (multiply partial product) if b(0) = 1 then adsh else sh end if;

15. seq_mult Datapath

16. mpp library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity mpp is generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); y1: out STD_LOGIC_VECTOR (width-1 downto 0); y2: out STD_LOGIC_VECTOR (width-1 downto 0) ); end mpp;

17. architecture mpp_arch of mpp is begin mp1: process(a,b,c) variable AVector: STD_LOGIC_VECTOR (width downto 0); variable CVector: STD_LOGIC_VECTOR (width downto 0); variable yVector: STD_LOGIC_VECTOR (width downto 0); begin AVector := '0' & a; CVector := '0' & c; if b(0) = '1' then yVector := AVector + CVector; else yVector := CVector; end if; y1 <= yVector(width downto 1); y2 <= yVector(0) & b(width-1 downto 1); end process mp1; end mpp_arch;

18. seq_mult Control

19. -- Title: Sequential Multiplier Control Unit library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity seq_mult_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; start, zdly: in STD_LOGIC; done, msel: out STD_LOGIC; aload, bload, cload, dload: out STD_LOGIC ); end seq_mult_control;

20. architecture seq_mult_control_arch of seq_mult_control is type state_type is (s0, s1, s2, s3); signal current_state, next_state: state_type; begin C1: process(current_state, start, zdly) begin

21. C1: process(current_state, start, zdly) begin case current_state is when s0 => if start = '1' then next_state <= s1; else next_state <= s0; end if; when s1 => next_state <= s2; when s2 => if zdly = '1' then next_state <= s3; else next_state <= s2; end if; when s3 => next_state <= s0; end case; end process C1;

22. statereg: process(clk, clr)-- the state register begin if clr = '1' then current_state <= s0; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process statereg;

23. C2: process(current_state, zdly) begin -- Initialize all outputs done <= '0'; aload <= '0'; bload <= '0'; cload <= '0'; dload <= '0'; msel <= '0'; case current_state is when s0 => null;

24. when s1 => msel <= '1';-- load a and b aload <= '1'; bload <= '1'; dload <= '1';-- reload delay count when s2 => msel <= '0';-- load b and c if zdly = '0' then bload <= '1'; cload <= '1'; end if; when s3 =>-- done done <= '1'; when others => null; end case; end process C2; end seq_mult_control_arch;

25. -- An n-bit down counter with load library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity delay_cnt is generic(width:positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; Z: out STD_LOGIC-- Z = 1 if q = 0 ); end delay_cnt; delay_cnt.vhd

26. architecture delay_cnt_arch of delay_cnt is signal q1: STD_LOGIC_VECTOR(width-1 downto 0); begin process(clk) begin if clr = '1' then for i in width-1 downto 0 loop q1(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if (load = '1') then q1 <= d; else q1 <= q1 - 1; end if; end process; delay_cnt.vhd (cont.)

27. process(q1) variable Zv: STD_LOGIC; begin Zv := '0'; for i in 0 to width-1 loop Zv := Zv or q1(i); -- Z = '0' if all q1(i) = '0' end loop; Z <= not Zv; end process; end delay_cnt_arch;

28. delay_cnt mux2g mpp a_reg b_reg c_reg seq_mult_ control

29. mpp

30. mux

31. -- Title: Multiply Test library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_unsigned.all; use work.mult_components.all; entity mult is port( mclk : in STD_LOGIC; bn : in STD_LOGIC; SW : in STD_LOGIC_VECTOR(1 to 8); BTN4: in STD_LOGIC; led: out std_logic; ldg : out STD_LOGIC; LD : out STD_LOGIC_VECTOR(1 to 8); AtoG : out STD_LOGIC_VECTOR(6 downto 0); A : out STD_LOGIC_VECTOR(3 downto 0) ); end mult; mult2.vhd

32. architecture mult_arch of mult is signal r, p, pout, x, b16, a16: std_logic_vector(15 downto 0); signal as, bs, ain, bin: std_logic_vector(7 downto 0); signal clr, clk, cclk, bnbuf, start, done: std_logic; signal clkdiv: std_logic_vector(26 downto 0); signal aload, bload, pload, dmsel: STD_LOGIC; signal m2sel: STD_LOGIC_VECTOR (1 downto 0); constant bus_width8: positive := 8; constant bus_width16: positive := 16;

33. begin U00:IBUFG port map (I => bn, O => bnbuf); led <= bnbuf; ldg <= '1'; -- enable 74HC373 latch clr <= bnbuf; -- Divide the master clock (50Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0);-- 25 MHz cclk <= clkdiv(17);-- 190 Hz

34. a16 <= "00000000" & as; b16 <= "00000000" & bs; U1: dmux2g generic map(width => bus_width8) port map (y => SW, a => ain, b => bin, sel => dmsel); U2a: reg generic map(width => bus_width8) port map (d => ain, load => aload, clr => clr, clk =>clk, q => as); U3b: reg generic map(width => bus_width8) port map (d => bin, load => bload, clr => clr, clk =>clk, q => bs); U4p: reg generic map(width => bus_width16) port map (d => p, load => pload, clr => clr, clk =>clk, q => pout);

35. U5: mux4g generic map(width => bus_width16) port map (a => a16, b => b16, c => pout, d => pout, sel => m2sel, y => r); U6: binbcd port map (B => r, P => x); U7: x7seg port map (x => x, cclk => cclk, clr => clr, AtoG => AtoG, A => A);

36. U8: mult_control port map (clr => clr, clk => clk, BTN4 => BTN4, mult_start => start, m2sel => m2sel, aload => aload, bload => bload, mult_done => done, dmsel => dmsel, pload => pload); U9: seq_mult generic map(width => bus_width8) port map (A => as, B => bs, clr => clr, clk =>clk, start => start, done => done, P => p); LD <= SW; end mult_arch;

37. Comparison to * No. of slicesNo. of Flip-flops 8 x 8 = 16 Combinational *79 (3%) 58 (1%) Sequential73 (3%) 92 (1%) 16 x 16 = 32 Combinational *95 (4%) 60 (1%) Sequential87 (3%) 109 (1%)