1. Built-In Self-Test and Calibration of Mixed-Signal Devices Ph.D Final Exam Wei Jiang Advisor: Vishwani D. Agrawal University Reader Minseo Park Committee Members: Fa F. Dai Victor P. Nelson Adit D. Singh March 24 2011

2. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam2

3. Motivation Digital BIST techniques – Defect-oriented – Logic BIST, scan chain, boundary scan, JTAG, etc Mixed-Signal BIST techniques – Specification-oriented – No universally accepted standard – Issues Parameter deviation Process variation Wei JiangGeneral Final Exam3

4. Approach Problem – Design a post-fabrication variation-tolerant process-independent technique for mixed-signal devices Solution – Test and characterize mixed-signal devices using digital circuitry – Use DSP as BIST controller for test pattern generation (TPG) and output data analysis (ORA) – Calibrate mixed-signal devices Wei JiangGeneral Final Exam4

5. Mixed-Signal Devices Both digital and analog circuitry in single die – DSP usually embedded for data processing – Analog circuitry controllable by digital part Converters – Analog-to-digital converter (ADC) Flash ADC, successive-approximation ADC, Pipeline ADC, Sigma-Delta ADC – Digital-to-analog converter (DAC) PWM/Oversampling DAC, Binary-weighted DAC Wei JiangGeneral Final Exam5

6. Testing of Mixed-Signal Devices Both digital and analog circuitry need test Defects and faults – Catastrophic faults (hard faults) – Parametric faults (soft faults) Test approaches – Functional test (specification oriented) – Structural test (defect oriented) Wei JiangGeneral Final Exam6

7. Digital BIST Conventional logic BIST technology LFSR-based random test; Scan-based deterministic test DSP can be TPG and ORA Digital circuitry must be fault-free before being used for mixed-signal test May be hardware or software based Wei JiangGeneral Final Exam7

8. Faulty Mixed-Signal Circuitry Good circuitry – All parameters and characteristics are within pre- defined specified range Fault-tolerance factor – Post-fabrication and software-controllable – Trade-off between fault-tolerance of parameter deviation and calibration resolution – Larger value for wider fixing range; smaller one for better fixing results – Fault-tolerance factor may vary for different applications Wei JiangGeneral Final Exam8

9. A Basic Digital BIST Architecture Wei JiangGeneral Final Exam9

10. Challenges Analog circuitry – No convincing fault model – Difficult to identify faults – Device parameters more susceptible to process variation than digital circuitry – Fault-free behavior based on a known range of acceptable values for component parameters Large statistical process variation effects in deep sub-micron MOSFET devices Wei JiangGeneral Final Exam10

11. Process Variation Parameter variation in nanoscale process Yield, reliability and cost Feature size scaling down and performance improvement Effects on digital and analog circuitry – Analog circuitry more affected by process variation – Parameter deviation severed in nanoscale process – System performance degraded when parameter deviation exceeds beyond tolerant limits Wei JiangGeneral Final Exam11

12. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam12

13. Resolution and Non-linearity Error Resolution: N-bit Least significant bit (LSB) Non-linearity errors – Differential non-linearity (DNL) – Integral non-linearity (INL) Wei Jiang13General Final Exam

14. Non-linearity Error of ADC Signal values at lower and upper edges of each codes Wei Jiang14General Final Exam

15. Non-linearity Error of ADC/DAC Wei JiangGeneral Final Exam15 Non-linearity error Non-linearity error

16. Noise and SNR Wei Jiang16General Final Exam

17. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam17

18. Typical Mixed-Signal Architecture Wei JiangGeneral Final Exam18

19. Mixed-Signal System Test Architecture Wei JiangGeneral Final Exam19 * F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

20. Test Architecture Digital system – Digital I/O, digital loopback – Digital signal processor (DSP) – TPG and ORA and test control unit Mixed-signal system – DAC and ADC, Analog loopback Analog system – Analog circuitry – Analog signal I/O, analog I/O loopback Wei JiangGeneral Final Exam20

21. Available Testing Approaches Servo-loop Method Oscillation BIST Method Sigma-Delta Testing Method FFT-based Testing Method Histogram Testing Method – Widely used for testing of on-chip ADC/DAC – Need large amount of samples and slow-gain current source – Unsuitable for high-resolution converters Wei JiangGeneral Final Exam21

22. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam22

23. Simplified Mixed-Signal System Wei Jiang23General Oral Examination

24. Proposed Approach Wei JiangGeneral Final Exam24

25. Testing Components Analog Signal Generator (ASG) – Linear ramp signals – Sinusoidal signals Measuring ADC (m-ADC) – High-resolution and high linearity – First-order single-bit Sigma-Delta ADC Dithering DAC (d-DAC) – Low resolution and low cost – Output voltage: specified error-tolerant range – Polynomial evaluation unit Wei JiangGeneral Final Exam25

26. Design of Ramp Signal Generator Wei JiangGeneral Final Exam26 Switch for resetting ramp II I/19.5 ΔV+Vth ΔVΔV Range: 0 v~ Vdd-ΔV Carefully chosen to make ΔV ≈ 0

27. Sinusoidal Testing Signal More complex design Used for dynamic testing (non-linearity (IP3), dynamic range, harmonic distortion) Fast Fourier Transformation (FFT) by DSP required Optional in the proposed BIST approach Wei JiangGeneral Final Exam27

28. Testing Components Measuring ADC (m-ADC) – First-order single-bit Sigma-Delta ADC – ENOB determined by oversampling ratio Dithering DAC (d-DAC) – Low resolution DAC: binary-weighted – Fault-tolerance factor Wei JiangGeneral Final Exam28

29. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam29

30. Testing Steps Diagnosis of testing components Testing of on-chip ADC using analog testing signals Testing of on-chip DAC using embedded DSP and measuring ADC Calibration of on-chip DAC using dithering DAC Validation of DAC calibration results using on- chip ADC/DAC Wei JiangGeneral Final Exam30

31. Diagnosis of Testing Components Wei JiangGeneral Final Exam31 *Assume non-linearities in signal generator and d-DAC do NOT match

32. Diagnosis of Testing Components ASG and m-ADC – Analog signal generated; usually linear ramp – m-ADC measures analog signals – DSP determines gain and offset of measurements d-DAC and m-ADC – DSP makes on-chip DAC output constant 0 – DSP generates digital test patterns; usually linear ramp – m-ADC measures d-DAC outputs – DSP determines gain and offset of measurements Only situation that fault undetected – ASG and d-DAC have exactly same non-linearity errors Wei JiangGeneral Final Exam32

33. Testing of ADC Similar to histogram testing method Wei JiangGeneral Final Exam33

34. Testing of ADC Divided full-range of ADC codes into two equal-size sections Sum up measurements of each section Lower bound M(0) and upper bound M(K) are discarded because of possible out-of-range measurements Wei JiangGeneral Final Exam34

35. Estimating Coefficients Wei JiangGeneral Final Exam35

36. Detailed Steps Reset ramp testing signal generator Detect first non-zero ADC output (lower-bound of samples) Measure all subsequent samples Stop at the maximum ADC output (upper-bound of samples) DSP collects all valid measurements and start to processing data Divide measured samples into two equal-size parts Accumulate measurements of each part to obtain two sums Calculate two syndromes from two sums Calculate two estimated coefficients of the linear ramp function (Optional) Compare each measured data to estimated one from ramp function Wei JiangGeneral Final Exam36

37. Simulation Results DNL and INLEstimation results Wei JiangGeneral Final Exam37

38. Other considerations Minimal number of samples – More samples, less quantization noise, more accurate estimation – Not all codes need to be sampled in order to reduce testing time – At least 2 N-2 samples are found necessary in practice The same idea may be used with low-frequency sinusoidal testing signals instead of ramp signal – More overhead and complexities with sinusoidal generator Wei Jiang38General Final Exam

39. Testing of DAC DSP as both TPG and ORA Wei JiangGeneral Final Exam39

40. Test of DAC Wei JiangGeneral Final Exam40

41. Components Digital circuitry (including DSP) as BIST control unit – Test pattern generation (TPG) and output response analysis (ORA) Measuring ADC – First-order 1-bit Sigma-Delta modulator – Digital low-pass filter – Measuring outputs of DAC-under-test Dither DAC (not used) – Low resolution DAC – Generating correcting signal for calibration – Calibrated DAC for test of ADC-under-test ADC Polynomial Fix (not used during testing) – Digital process to revise ADC output codes Wei JiangGeneral Final Exam41

42. Polynomial Fitting Algorithm Introduced by Sunter et al. in ITC’97 and A. Roy et al. in ITC’02 Summary: – Divide DAC transfer function into four sections – Combine function outputs of each section (S0, S1, S2, S3) – Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations Wei JiangGeneral Final Exam42

43. Third-order Polynomial Offset Gain And Harmonic Distortion Wei JiangGeneral Final Exam43

44. Simulation Results INL of 14-bit DAC Results of fitting polynomial Wei JiangGeneral Final Exam44 Oversampling ratio for m-ADC

45. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam45

46. Calibration of DAC Wei JiangGeneral Final Exam46 The output of calibrated DAC can be considered as linear

47. Dithering DAC low- resolution DAC Better linearity output with DEM Must be tested by measuring ADC before test of on- chip mixed- signal devices Wei JiangGeneral Final Exam47 3 α =1 17bits Resolution of dithering-DAC (bits) Estimated DAC resolution (bits) Oversampling ratio (OSR) 2

48. Polynomial Evaluation Either hardware or software implementation Hardware Implementation – Faster and DSP not occupied – High overhead due to huge block of digital multiply circuit Software Implementation – DSP drives both on-chip DAC and dithering DAC with calculated value – Performance penalty Wei JiangGeneral Final Exam48

49. Simulation Results d-DAC errorsCalibration results Wei JiangGeneral Final Exam49

50. Verification of ADC/DAC Wei JiangGeneral Final Exam50 *OPTIONAL

51. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam51

52. Measuring ADC First-order single-bit sigma-delta ADC Diagnosis performed before mixed-signal test In-band quantization noise moved up due to oversampling and noise shaping Higher-order multiple-bit Sigma-Delta ADC can also be used Wei JiangGeneral Final Exam52

53. Sigma-Delta Modulator First-order single-bit Diagram Transfer function Wei JiangGeneral Final Exam53

54. Oversampling and Noise shaping Wei JiangGeneral Final Exam54 * F. F. Dai and C. E. Stroud, “ ΣΔ Modulation for Factional-N Synthesis ” Chapter 9, p. 307 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.

55. Sigma-Delta Modulator Oversampling Ratio Signal-to-noise-distortion Ratio Signal-to-noise Ratio First-order Wei JiangGeneral Final Exam55

56. Sigma-Delta Modulator Second-order Higher order Wei JiangGeneral Final Exam56

57. Select Proper Order Wei JiangGeneral Final Exam57 First-order Second-order Third-order 17-bit ENOB 104.1LSB Oversampling ratio (OSR) SNR (LSB)

58. Multiple Bits N: NOB of quantizer n: order of ΣΔ modulator Wei JiangGeneral Final Exam58

59. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam59

60. Polynomial Fitting Different order of fitting polynomial can be used for various applications – Linear fitting – Second-order fitting – Third-order fitting – Higher order fitting Computation complexity and hardware overhead increase exponentially Wei JiangGeneral Final Exam60

61. Linear Fitting Wei JiangGeneral Final Exam61

62. Second-order Fitting Wei JiangGeneral Final Exam62

63. Second-order Fitting Wei JiangGeneral Final Exam63

64. Third-order Fitting Wei JiangGeneral Final Exam64

65. Comparison of different orders Wei JiangGeneral Final Exam65

66. Higher-Order Fitting Possibly better fitting result Impractical for hardware implementation due to huge overhead Expressions on calculation of coefficients can be derived in the same way Usually third-order polynomial fitting is sufficient for the most applications Wei JiangGeneral Final Exam66

67. Adaptive Polynomial Fitting Dynamically choose polynomial degree Low-order polynomial – Simple to design and implement – Less area and performance overhead – Large fitting error High-order polynomial – Better fitting results – More coefficients to store – Much more complicated polynomial evaluation circuitry design and heavy area and performance overhead Wei JiangGeneral Final Exam67

68. Implementation Analog Signal Generator (ASG) – A few transistors; low overhead Measuring ADC (m-ADC) – First-order 1-bit Sigma-Delta ADC; low overhead Dithering DAC (d-DAC) – Low resolution DAC; low overhead Polynomial Evaluation Unit (HW) – Multiply-accumulate Logic; huge overhead Wei JiangGeneral Final Exam68

69. Truncation Error Wei JiangGeneral Final Exam69 12-bit is sufficient for a10-bit DAC (above); 16-bit for 12-bit DAC (below) Truncation Error (LSB) LinearSecond-orderThird-orderHigher 4-bit64.29677.47484.620188.622 8-bit3.24275.01055.81876.2390 12-bit00.283520.372170.40544 16-bit00.0108210.0235780.025812 Truncation Error (LSB) LinearSecond-orderThird-orderHigher 4-bit255.30309.60337.97354.91 8-bit15.25120.35823.17025.054 12-bit01.25151.49931.6491 16-bit00.0708150.0947110.10523

70. Truncation Error Truncation Error (LSB) LinearSecond-orderThird-orderHigher 4-bit1023.31237.91351.31419.5 8-bit63.25281.18192.521100.141 12-bit3.24055.12445.97946.5742 16-bit00.312800.377200.42131 20-bit00.0177000.0237810.026617 24-bit00.000675590.00148190.0016703 Wei JiangGeneral Final Exam70 * 16-bit is sufficient for calibration of a14-bit DAC; 17-bit could be better

71. Hardware Overhead Wei JiangGeneral Final Exam71 Overhead (Gates/DFFs) LinearSecond-orderThird-orderHigher 4-bit21638495878661531329235 8-bit3576386315215562752334430 12-bit52092128122623224103642643 16-bit658116164629130095314743837 20-bit8201452064364377566672181274 24-bit9591692432429446478885801514 * Synthesized with TSMC018 library; approximately in count of NAND2/DFFX1

72. Testing Time Variables – N: resolution of on-chip ADC/DAC – T: sample/conversion time of ADC/DAC – M: OSR for Sigma-Delta modulator – N’: resolution of d-DAC Example – 14-bit ADC/DAC with 10ns conversion time – Oversampling ratio of ΣΔ is 2000 –6-bit d-DAC for calibration Wei JiangGeneral Final Exam72

73. Testing Time Diagnosis – ASG and m-ADC: T d1 – d-DAC and m-ADC: T d2 Test of ADC: T ad Test of DAC: T da Verification of ADC/DAC: T v Total testing time: –Assume T=10ns, M=2000,N=14, N’=6 –Total time = 657ms Wei JiangGeneral Final Exam73

74. Outline Introduction Background BIST Architecture for Mixed-Signal Devices – Overview of Proposed Architecture – Test of DAC/ADC – Calibration of DAC Sigma-Delta Modulation Polynomial Fitting Algorithm Conclusion Wei JiangGeneral Final Exam74

75. General Mixed-Signal Test Variation-tolerant design Digital controlled BIST Digitalized TPG/ORA Self-testable measuring components Characterization of device-under-test by DSP Faulty circuitry determined by characterized parameters Coefficients of output fix/correction signals calculated by DSP Wei JiangGeneral Final Exam75

76. Conclusion A post-fabrication built-in test and calibration approach for mixed-signal devices is proposed This approach relies on digital circuitry and DSP for TPG/ORA and BIST control Digital circuitry is testable by conventional digital testing approaches and therefore guarantee the testability of analog circuitry On-chip ADC/DAC are tested separately and verified Calibration on mixed-signal devices will significantly reduce defects, improve die yield and lower manufacturing cost Wei JiangGeneral Final Exam76

77. Publications W. Jiang and V. D. Agrawal, “Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC,” NATW’08, pp. 61-68. W. Jiang and V. D. Agrawal, “Built-in Self-Calibration of On-Chip DAC and ADC,” ITC’08, paper 32.2. W. Jiang and V. D. Agrawal, “Built-in Adaptive Test and Calibration of DAC,” NATW’09, pp. 3-8. W. Jiang and V. D. Agrawal, “Designing Variation-Tolerance in Mixed-Signal Components of a System-on-Chip,” ISCAS’09, pp. 126-129. W. Jiang and V.D. Agrawal, “A DSP-Based Ramp Test for On-Chip High-Resolution ADC,” ICIT’11

78. References M. L. Bushnell and V. D. Agrawal, “Essentials of Testing for Digital, Memory, & Mixed-Signal VLSI Circuits,” Boston: Springer, 2000 F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architecture,” Morgan kaufmann, 2008. S. Sunter and N. Nagi, “A Simplified Polynomial Fitting Algorithm for DAC and ADC BIST,” ITC’97, pp.389-395 A. Roy, S. Sunter et al., “High Accuracy Stimulus Generation for A/D Converter BIST,” ITC’02, pp.1031-1039 Wei JiangGeneral Final Exam78

79. THANK YOU Wei Jiang79General Final Exam