1. 1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Winter 2005 Winter 2005 Virtex II-Pro Dynamical Test Application - Part B -

2. 2 Quick Overview Examining possible space-compatibility of civilian devices, in order to integrate them in satellites. Examining possible space-compatibility of civilian devices, in order to integrate them in satellites. Statistically modeling the device ’ s robustness to temporary damage and it ’ s ability to recover in a case of an error. Statistically modeling the device ’ s robustness to temporary damage and it ’ s ability to recover in a case of an error. Testing the device ’ s modules functioning under real-time radiation. Testing the device ’ s modules functioning under real-time radiation.

3. 3 THE COMPLETE SYSTEM OVERVIEW HOST - PC DUT - Virtex II-PRO XC2VP7 (placed on the development board) Serial Port USB Port JTAG Port

4. 4 System Block Diagram DUT Virtex II-PRO FPGA Virtex II-PRO FPGA Host Xilinx Tools GUI Microsoft Excel Logic Power PC Serial Port USB Port JTAG Port

5. 5 The Virtex II-PRO FPGA XC2VP7 The Internal FPGA Modules: - 8 Rocket I/O Transceiver Blocks - 4 DCM (Digital Clock Manager) - 44 Block Select RAM Memory total of 792KB - 44 18x18 Multiplier Blocks - PPC405 - 396 User I/O pads - 4928 slices holding 157KB memory, 9856 flip-flops, and 11088 logic cells DUT Host

6. 6 Graphical User Interface User transparent User transparent Initializing the testing system Initializing the testing system Choosing and loading the testing function Choosing and loading the testing function Receiving data via USB and calculating statistical results Receiving data via USB and calculating statistical results GUI was created in C++ language, using Visual Studio 6 GUI was created in C++ language, using Visual Studio 6 Uses supplied Dynamic Library files (Dll files), Uses supplied Dynamic Library files (Dll files), in order to control the USB module in order to control the USB module DUT Host

7. 7 Graphical User Interface - Algorithm Test in Process Gathering test info Writing appropriate impl. file Test type decision Opening USB port Sending start signal Listening to USB Collecting data to Excel file Closing USB port Delete temporary var. End Test condition Opening Excel START Test Ended DUT Host

8. 8 GUI – Main Window Status Window Test Type Tests List DUT Host

9. 9 GUI – Settings Window Programs ’ location USB connection & drivers check button DUT Host Serial Port COM Select

10. 10 Serial Port JTAG Port Host DUT - Virtex II-PRO FPGA DUT - Virtex II-PRO FPGA Power PC Power PC USB Port DUT - Virtex II-PRO FPGA DUT - Virtex II-PRO FPGA LOGIC JTAG Port Host The DUT Combined of: Power PC Power PC Logic – logic and memory elements, DCM, MGT. Logic – logic and memory elements, DCM, MGT. In the Power PC tests the Serial Port is being used. In the Logic tests the USB Port is being used. The first part of this presentation deals with the LOGIC modules of the FPGA and the USB connection …

11. 11 DLP-USB245M - Features Fast connection – up to 1 Mb/sec. Fast connection – up to 1 Mb/sec. Small implementation Small implementation Simple Interface Simple Interface Mounted on a P130 expansion module Mounted on a P130 expansion module DUT Host

12. 12 The Testing Concept – Peripheral Modules

13. 13 MUT - Module Under Test The examined modules: I/O Blocks I/O Blocks Fast Multipliers Fast Multipliers Rocket I/O Rocket I/O Digital Clock Manager (DCM) Digital Clock Manager (DCM) CLB Memory CLB Memory CLB Flop-flops CLB Flop-flops CLB logic CLB logic BRAMs BRAMs Power PC Power PC USB Contr. MCT MUT

14. 14 USB Controller USB Contr. MCT MUT Controls reading and writing cycles. Controls reading and writing cycles. Determines USB ’ s control signals during reading and writing cycles. Determines USB ’ s control signals during reading and writing cycles. Sets up the relevant data to be sent back to host. Sets up the relevant data to be sent back to host. Designed with minimal usage of logic and memory elements. Designed with minimal usage of logic and memory elements.

15. 15 USB Controller USB Contr. MCT MUT

16. 16 MCT Identical basic structure for all the testing functions: Identical basic structure for all the testing functions: - Defines input and comparison vectors in order to test the - Defines input and comparison vectors in order to test the module ’ s functioning. module ’ s functioning. - Computes the numbers of errors and instructs their - Computes the numbers of errors and instructs their transference using the USB Controller. transference using the USB Controller. Designed with the ambition to maximize the test ’ s mapping of each examined module. Designed with the ambition to maximize the test ’ s mapping of each examined module. Minimal usage of logic and memory elements. Minimal usage of logic and memory elements. USB Contr. MCT MUT

17. 17 The MCT Testing Flow End Test Command Creating input and comparison vectors; Updating control signals Listening to Host Single/ Multiple tests? Waiting for outputs Sending input vectors to MUT Multiple tests Checking outputs; Sending results Single test Loading bit file Test Ended

18. 18 The Fast Multipliers Test USB Contr. MCT MUT USB Controller MCT MUT (Multiplier Blocks) Reading Control Read-Write Control Writing Control * Error Generator * Indicator Reset Block

19. 19 Several blocks of fast multipliers are chained together to achieve 100% mapping. Several blocks of fast multipliers are chained together to achieve 100% mapping. The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are being compared with the expected result vectors using several feedbacks. The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are being compared with the expected result vectors using several feedbacks. The calculated errors are being sent via USB, using the USB Controller, in steady time intervals. The calculated errors are being sent via USB, using the USB Controller, in steady time intervals. Same method of diffusion through the MUT blocks chain and of error calculation by comparison between the expected result vectors and the output vectors was used in all the performed tests described further … Same method of diffusion through the MUT blocks chain and of error calculation by comparison between the expected result vectors and the output vectors was used in all the performed tests described further … The Fast Multipliers Test USB Contr. MCT MUT

20. 20 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 1,229 out of 9,856 12% Number of 4 input LUTs: 1,796 out of 9,856 18% Logic Distribution: Number of occupied Slices: 1,352 out of 4,928 27% Total Number 4 input LUTs: 1,820 out of 9,856 18% Number of bonded IOBs: 13 out of 248 5% Number of PPC405s: 0 out of 1 0% Number of MULT18X18s: 44 out of 44 100% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% Fast Multipliers Test Mapping Statistics:

21. 21 The BRAMs Test USB Contr. MCT MUT USB Controller MCT MUT (BRAM Block) Reading Control Read-Write Control Writing Control Indicator Reset Block

22. 22 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 150 out of 9,856 1% Number of 4 input LUTs: 405 out of 9,856 4% Logic Distribution: Number of occupied Slices: 245 out of 4,928 4% Total Number 4 input LUTs: 420 out of 9,856 4% Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of Block RAMs: 44 out of 44 100% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% BRAMs Test Mapping Statistics:

23. 23 CLB Flip-Flops Test USB Contr. MCT MUT USB Controller MCT MUT (CLB Flip-Flops Blocks) Indicator Reset Block

24. 24 CLB Flip-Flops Test USB Contr. MCT MUT CLB Flip-Flops Block – Closer Look

25. 25 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 9,235 out of 9,856 93% Number of 4 input LUTs: 227 out of 9,856 2% Logic Distribution: Number of occupied Slices: 4,926 out of 4,928 99% Total Number 4 input LUTs: 237 out of 9,856 2% Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% CLB Flip-FlopsTest Mapping Statistics: CLB Flip-Flops Test Mapping Statistics:

26. 26 CLB Logic Test USB Contr. MCT MUT USB Controller MCT MUT (Logic Blocks - Adders) Reading Control Read-Write Control Writing Control Indicator Reset Block

27. 27 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 9,705 out of 9,856 98% Number of 4 input LUTs: 6,188 out of 9,856 62% Logic Distribution: Number of occupied Slices: 4,926 out of 4,928 99% Total Number 4 input LUTs: 6,188 out of 9,856 62% Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% CLB LogicTest Mapping Statistics: CLB Logic Test Mapping Statistics:

28. 28 CLB Memory Test USB Contr. MCT MUT USB Controller MCT MUT (LUT Blocks) Indicator Reset Block

29. 29 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 128 out of 9,856 1% Number of 4 input LUTs: 1,047 out of 9,856 10% Logic Distribution: Number of occupied Slices: 4,920 out of 4,928 99% Total Number 4 input LUTs: 9,760 out of 9,856 99% Number used for 32x1 RAMs: 8,704 (Two LUTs used per 32x1 RAM) Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of GCLKs: 1 out of 16 6% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% CLB MemoryTest Mapping Statistics: CLB Memory Test Mapping Statistics:

30. 30 DCM Test USB Contr. MCT MUT USB Controller MCT MUT (4 DCM Units) Indicator Reset Block

31. 31 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 272 out of 9,856 2% Number of 4 input LUTs: 452 out of 9,856 4% Logic Distribution: Number of occupied Slices: 273 out of 4,928 5% Total Number 4 input LUTs: 452 out of 9,856 4% Number of bonded IOBs: 18 out of 248 7% Number of PPC405s: 0 out of 1 0% Number of GCLKs: 16 out of 16 100% Number of DCMs: 4 out of 4 100% Number of GTs: 0 out of 8 0% Number of GT10s: 0 out of 0 0% DCMTest Mapping Statistics: DCM Test Mapping Statistics:

32. 32 Rocket I/O Test USB Contr. MCT MUT USB Controller MCT MUT (Transceivers Block) Indicator Reset Block Clock Buffers

33. 33 Rocket I/O Test USB Contr. MCT MUT DATA FLOW CHART – Transceivers and Loop-back Testing

34. 34 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 117 out of 9,856 1% Number of 4 input LUTs: 294 out of 9,856 2% Logic Distribution: Number of occupied Slices: 186 out of 4,928 3% Total Number 4 input LUTs: 294 out of 9,856 2% Number of bonded IOBs: 26 out of 248 10% Number of PPC405s: 0 out of 1 0% Number of GTIPADs: 8 out of 16 50% Number of GTOPADs: 8 out of 16 50% Number of GCLKs: 1 out of 16 6% Number of GTs: 4 out of 8 50% Number of GT10s: 0 out of 0 0% Rocket I/O Transceivers Test Mapping Statistics:

35. 35 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 119 out of 9,856 1% Number of 4 input LUTs: 389 out of 9,856 3% Logic Distribution: Number of occupied Slices: 229 out of 4,928 4% Total Number 4 input LUTs: 389 out of 9,856 3% Number of bonded IOBs: 26 out of 248 10% Number of PPC405s: 0 out of 1 0% Number of GTIPADs: 16 out of 16 100% Number of GTOPADs: 16 out of 16 100% Number of GCLKs: 1 out of 16 6% Number of GTs: 8 out of 8 100% Number of GT10s: 0 out of 0 0% Rocket I/OTest Mapping Statistics: Rocket I/O Loop-Back Test Mapping Statistics:

36. 36 Combined Test USB Contr. MCT MUT USB Controller MCT Reading Control Read-Write Control Writing Control Indicator Reset Block CLB Logic (adders) Fast Multipliers MGT DCM CLB Memory (LUTs) BRAMs

37. 37 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 8,661 out of 9,856 87% Number of 4 input LUTs: 7,137 out of 9,856 72% Logic Distribution: Number of occupied Slices: 4,926 out of 4,928 99% Total Number 4 input LUTs: 7,655 out of 9,856 77% Number of bonded IOBs: 26 out of 248 10% Number of PPC405s: 0 out of 1 0% Number of GTIPADs: 16 out of 16 100% Number of GTOPADs: 16 out of 16 100% Number of Block RAMs: 44 out of 44 100% Number of MULT18X18s: 44 out of 44 100% Number of GCLKs: 1 out of 16 6% Number of GTs: 8 out of 8 100% Number of DCMs: 1 out of 4 25% Number of GT10s: 0 out of 0 0% CombinedTest Mapping Statistics: Combined Test Mapping Statistics:

38. 38 SOFTWARE WORK FLOW Bit file GUI Design Logic Simulation High Level Design Core Generator, Architecture Wizard Low Level Synthesis Test Algorithm Place and Route

39. 39 The Virtex II-Pro FPGA XC2VP7 Power-PC 405 structure DUT Host

40. 40 Performed Tests 1. General Purpose Registers test 2. MMU test (TLB) 3. Instruction test (including memory test) 4. Cache test 5. Timers test 6. Interrupts test 7. Integrated modules test

41. 41 Hardware Design: 3 Hardware platforms: Hardware Design: 3 Hardware platforms: 1. Platform without access to external memory – for cache test 2. Platform with maximum modules – for integrated modules test 3. Platform with minimum modules – for all other tests Software design: 2 layers - C code & assembly Software design: 2 layers - C code & assembly Implementation of software in designated BRAM block Implementation of software in designated BRAM block Test Concept - PPC

42. 42 Hardware Design – Block Diagram PPC 405 PLB PLB2OPB BRAM OPB JTAG Timer RS232 (UART) DCM To Host

43. 43 Hardware Design – Block Diagram Cache test system PPC 405 PLB PLB2OPB BRAM OPB JTAG Timer RS232 (UART) DCM To Host

44. 44 Hardware Design – Block Diagram Integrated test system PPC 405 PLB PLB2OPB BRAM BRAM OPB JTAG Timer RS232 (UART) DCM To Host GPIO

45. 45 Test Algorithm - PPC Assembly Layer Assembly Layer C code Layer START Create Input & “ Golden ” Vectors Assign Physical Address To inputs Load input Vectors by physical address Perform Test Create Outputs Save output Vectors to specified Physical address Load & Compare Outputs with golden vectors Send results to serial port Single/ Multiple tests? FINISH TEST

46. 46 Write the following values to registers: 0x00000000,0xFFFFFFFF,0xAAAAAAAA,0x55555555, Number of register (0-31). Read from registers and compare to written values Instructions Used: li, mr, addi 1. General-Purpose Registers

47. 47 TLB buffer contains 64 indexes. Using same method as in the General-Purpose Registers test for the TLB Buffer. Write & read to each index Instructions Used: tlbre, tlbwe 2. MMU Test - TLB

48. 48 3. Instruction Set Executing selected instructions (including memory instructions) using above values. Compare outputs with those expected. Instructions tested: Arithmetic: Add, mulli, subf Compare: cmpi, mfcr Logic: Or, And, Xor Memory: stw, lwz Branch: b

49. 49 As mentioned – a separate hardware platform is used here. Run simple code which performs Add, Multiply and Condition operations. Compare with expected results. C-Code level only. No special instructions used. C-Code level only. No special instructions used. 4. Cache Test

50. 50 5. Timers test Implement a timer (using base system resources), and Measure a pre-defined process. Compare with expected results. C-Code level only. No special instructions used. C-Code level only. No special instructions used. access to timer using supplied driver.

51. 51 Generating an Interrupt which raise a global flag and Check the flag ’ s value. The interrupt is generated using decrementing counter (based on a timer implemetation) C-Code level only. No special instructions used. C-Code level only. No special instructions used. access to timer and control on interrupt using supplied driver. 6. Interrupts test

52. 52 As mentioned – a separate hardware platform is used here. Run simple but common program which generate outputs. Then compare results with those expected. 6. Integrated Modules test

53. 53 Example Code - TLB main() { int* a; int* addr; int i,errors; a=(int*)0x00000010; *a=0x00000000; errors=0; li(2,0x00000010); lwz(2,2); li(3,0); for(i=0;i<63;i++){ tlbwe(2,3,0); tlbwe(2,3,1); addi(3,3,1);} li(2,0x00000100); li(3,0); for(i=0;i<63;i++){ tlbre(4,3,0); addi(4,4,0); stw(4,2); addi(2,2,4); tlbre(4,3,1); stw(4,2); addi(2,2,4); addi(3,3,1);} for(i=0;i<63;i++){ addr=(int*)(256+4*i); if(0x00000000!=*addr){ errors++;} xil_printf( “ %d ”,errors); } } } } } } } } Initialize Test Initialize Write Process Write Process Initialize Read Process Read Process Compare Process Send result to host

54. 54 1. Design the hardware structure (MHS file) 2. Create hardware platform (MMS file - Platgen stage) 3. Create software platform, i.e. designated drivers, parameters, libraries etc. (Libgen stage) 4. Design software (C-Code) 5. Compile software (ELF file) 6. Combine HW & Software (BIT file) 7. Download to device and run (Impact) Work Flow – Xilinx EDK

55. 55 Design Tools Used During The Project HDL Designer – Creating hardware applications HDL Designer – Creating hardware applications MODELSIM – VHDL simulation MODELSIM – VHDL simulation Synplify – Synthesis tool Synplify – Synthesis tool Xilinx ISE Project Navigator – Place and Route Xilinx ISE Project Navigator – Place and Route Xilinx XPS (EDK) – PPC related tests Xilinx XPS (EDK) – PPC related tests Visual C++ – Designing the GUI Visual C++ – Designing the GUI