1. Analysis and Avoidance of Cross-talk in on-chip buses Chunjie Duan Ericsson Wireless Communications Anup Tirumala Jasmine Networks Sunil P Khatri University of Colorado, Boulder

2. Outline  Introduction  Classification of Cross-talk types  Eliminating 3C and 4C sequences  Eliminating 4C sequences  Experimental Results  Conclusions

3. Introduction  Verified cross-talk trends  Accurate 3-D capacitance extraction  Delay variation 2.47:1 (200  m wires, 10X drivers, 0.1  m technology)  Deep sub-micron process s t w a v a CICI CLCL v a CLCL CLCL CICI a v a CLCL v a CLCL CICI CICI CLCL a a v a CLCL v CLCL CLCL CICI CICI a CICI a a v v CICI CLCL CLCL CLCL CICI CICI CLCL CLCL CLCL CICI CLCL CICI CLCL CLCL

4. Cross-talk vs Bus Data Pattern  When λ ~ 0.1μm, r = C I /C L > 10 (metal 4)  Effective total capacitance depends on bus data sequence :  Best case: 0 x C I x L  Worst case: 4 x C I x L 0·C I C total = 0 ·C I C total = 4 ·C I 0·C I 2·C I

5. Classification of Cross-talk  4·C sequence:  3·C sequence  2·C sequence  1·C sequence  0·C sequence  Forbidden patterns (“010” and “101”)

6. Eliminating 3C & 4C Sequences  Motivation  Maximum bus data rate depends on total capacitance seen by any bit  Removing 3C and 4C sequences will increase the maximum data rate  Simple approach: shielding  g s g s g s g... (ground line between signals)  No 3C or 4C sequences possible  However, bus-width is doubled  Coding gain = (throughput/area) with coding (throughput/area) without coding  Coding gain = 0 for this approach - 1

7. Eliminating 3C & 4C Sequences  Theorem: If no forbidden patterns are allowed on the bus,  Proof: see paper  Our approach:  Encode the data on the bus to get rid of the forbidden patterns  Questions to be answered:  What is the number of redundancy bits (and the coding gain)?  How to practically implement such a CODEC ?

8. Number of Redundancy Bits  Map the n bit bus to a k=n+r bit bus so that  the k bit data bus has no forbidden patterns  Definitions :  T(n): number of distinct n-bit vectors.  T(n)=2 n  T B (n): number of n-bit vectors which contain a forbidden pattern  T G (n): number of n-bit vectors which do not contain forbidden patterns  Let the sets of vectors be V(n), V B (n), and V G (n) respectively  Let v(n), v B (n) and v G (n) respectively represent an element of these sets  T GG (n): Number of n-bit vectors in V G (n) with last 2 bits ‘00’ or ‘11’  T GB (n): number of n-bit vectors in V G (n) with last two bits ‘01’ or ‘10’  Goal: to find the smallest k such that

9. Counting Forbidden Vectors  v(n) can be constructed by appending {0,1} to any v(n-1)  Two v(n) are constructed from any v(n-1)  Two v B (n) are constructed from any v B (n-1)  xxx010xx -> xxx010xx0, xxx010xx1  One v GG (n) and one v GB (n) are constructed from any v GG (n-1)  xxxxxx00 -> xxxxxx000, xxxxxx001  One v GG (n) and one v B (n) are constructed from any v GB (n-1)  xxxxxx01 -> xxxxxx010, xxxxxx011

10. Counting Forbidden Vectors  Algorithm  Initial conditions (n=3)  T(3) = 8, T G (3) = 6, T B (3)=2, T GG (3)=4, T GB (3)=2  Inductive step  T(n) = 2 x T(n-1);  T G (n) = 2 x T G (n-1) + T G (n-1)  T GG (n) = T GG (n-1) + T GB (n-1)  T B (n) = 2 x T B (n-1) + T GB (n-1)

11. Eliminating 3C & 4C sequences  44% overhead when n > 30 bits  Coding gain

12. 3C & 4C CODEC Implementation  Implements a one-to-one map from V(n) to V G (k)  Look-Up Table, straightforward, can achieve minimum overhead (44%), but not practical  Our implementation  62.5% overhead (higher than minimum)  Modular and straightforward  Break bus into 4-bit groups  Encode each group independently (4bit -> 5 bit)  Additional logic to handle across-the-boundary forbidden patterns  Ripple effect (Eliminated by pipelining)

13. 3C & 4C CODEC Implementation CODEC block diagram b0b1b2b3b0b1b2b3 b4b5b6b7b4b5b6b7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15

14. Eliminating 4C sequences  Less aggressive: eliminating 4C sequences only  Less overhead (33%) : simpler implementation  Simpler algorithm  Divide the bus into 3 bit groups  When 4C sequence occurs, complement group data  Insert group complement indicator  Special handling for across-the-boundary forbidden sequences (see paper for details)  Examples:  101 001 -> 010 010  1010 0010 -> 1011 0100

15. Experimental Results  Bus simulations  CODEC was not modeled  Spice3, 0.1μm model  Transmission line with inter-wire coupling  Quantify delay dependency on bus vector sequences  CODEC implementation  Currently implemented 3C & 4C CODEC  Matching delay on CODEC outputs  4C CODEC implementation planned in future

16. Bus Simulation Results  Bus length 5mm, 10mm or 20mm  Driver strength 30X, 60X and 120X of minimum

17. CODEC Results  Compare waveform with coding and w/o coding  Random input sequence Random sequence Recovered sequence encoderdecoder driver receiver Random sequence Recovered sequence encoderdecoder driver receiver  Encoder/decoder delay ~250ps  Max data rate more than 2X compared to scheme with no encoding

18. CODEC Results  random sequence directly into bus buffer  20mm trace  45x buffer  > 1ns delay variation  Random sequence into 3C & 4C encoder  20mm trace  45x buffer  < 500ps delay variation

19. Experimental Results Reshaped data after receivers  without coding,  edge jitter ~ 1000ps  with coding  edge jitter < 500ps

20. Conclusions  Inter-wire capacitance increasingly significant in DSM VLSI interconnect  Total capacitance is heavily dependent on bus data sequence  With 44% overhead, we can eliminate 3C & 4C cross- talk  Compared to shielding, which has 100% overhead  Implemented CODEC to eliminate 3C and 4C cross- talk sequences  Proposed CODEC to eliminate 4C cross-talk sequences with 33% overhead  Simulation results match our analysis.

21. Thank You!