1. Penn ESE535 Spring 2009 -- DeHon 1 ESE535: Electronic Design Automation Day 17: March 30, 2009 Clustering (LUT Mapping, Delay)

2. Penn ESE535 Spring 2009 -- DeHon 2 Background Question Experience with FPGAs? What provides programmable logic in an FPGA?

3. Penn ESE535 Spring 2009 -- DeHon 3 Today How do we map to LUTs? What happens when delay dominates? Lessons… –for non-LUTs –for delay-oriented partitioning

4. Penn ESE535 Spring 2009 -- DeHon 4 LUT Mapping Problem: Map logic netlist to LUTs –minimizing area –minimizing delay Old problem? –Technology mapping? (Last Monday) –How big is the library? 2 2 K gates in library

5. Penn ESE535 Spring 2009 -- DeHon 5 Simplifying Structure K-LUT can implement any K-input function

6. Penn ESE535 Spring 2009 -- DeHon 6 Cost Function Delay: number of LUTs in critical path –doesn’t say delay in LUTs or in wires –does assume uniform interconnect delay Area: number of LUTs –Assumes adequate interconnect to use LUTs

7. Penn ESE535 Spring 2009 -- DeHon 7 LUT Mapping NP-Hard in general Fanout-free -- can solve optimally given decomposition –(but which one?) Delay optimal mapping achievable in Polynomial time Area w/ fanout NP-complete

8. Penn ESE535 Spring 2009 -- DeHon 8 Preliminaries What matters/makes this interesting? –Area / Delay target –Decomposition –Fanout replication reconvergent

9. Penn ESE535 Spring 2009 -- DeHon 9 Area vs. Delay

10. Penn ESE535 Spring 2009 -- DeHon 10 Decomposition

11. Penn ESE535 Spring 2009 -- DeHon 11 Decomposition

12. Penn ESE535 Spring 2009 -- DeHon 12 Fanout: Replication

13. Penn ESE535 Spring 2009 -- DeHon 13 Fanout: Replication

14. Penn ESE535 Spring 2009 -- DeHon 14 Fanout: Reconvergence

15. Penn ESE535 Spring 2009 -- DeHon 15 Fanout: Reconvergence

16. Penn ESE535 Spring 2009 -- DeHon 16 Monotone Property Does cost function increase monotonicly as more of the graph is included? (do all subsets have property) –gate count? –I/o? Important? –How far back do we need to search?

17. Penn ESE535 Spring 2009 -- DeHon 17 Definition Cone: set of nodes in the recursive fanin of a node

18. Penn ESE535 Spring 2009 -- DeHon 18 Example Cones

19. Penn ESE535 Spring 2009 -- DeHon 19 Delay

20. Penn ESE535 Spring 2009 -- DeHon 20 Dynamic Programming Optimal covering of a logic cone is: –Minimum cost (all possible coverings) Evaluate costs of each node based on: –cover node –cones covering each fanin to node cover Evaluate node costs in topological order Key: are calculating optimal solutions to subproblems –only have to evaluate covering options at each node

21. Penn ESE535 Spring 2009 -- DeHon 21 Flowmap Key Idea: –LUT holds anything with K inputs –Use network flow to find cuts  logic can pack into LUT including reconvergence …allows replication –Optimal depth arise from optimal depth solution to subproblems

22. Penn ESE535 Spring 2009 -- DeHon 22 MaxFlow Set all edge flows to zero –F[u,v]=0 While there is a path from s,t –(breadth-first-search) –for each edge in path f[u,v]=f[u,v]+1 –f[v,u]=-f[u,v] –When c[v,u]=f[v,u] remove edge from search O(|E|*cutsize) Day 10

23. Penn ESE535 Spring 2009 -- DeHon 23 Delay objective: –minimum height, K-feasible cut –I.e. cut no more than K edges –start by bounding fanin  K Height of node will be: –height of predecessors or –one greater than height of predecessors Check shorter first Flowmap 11 11 2

24. Penn ESE535 Spring 2009 -- DeHon 24 Flowmap Construct flow problem –sink  target node being mapped –source  start set (primary inputs) –flow infinite into start set –flow of one on each link –to see if height same as predecessors collapse all predecessors of maximum height into sink (single node, cut must be above) height +1 case is trivially true

25. Penn ESE535 Spring 2009 -- DeHon 25 11 2 2 1 1 Example Subgraph Target: K=4

26. Penn ESE535 Spring 2009 -- DeHon 26 3 11 2 2 1 1 Trivial: Height +1

27. Penn ESE535 Spring 2009 -- DeHon 27 11 2 2 1 1 Collapse at max height

28. Penn ESE535 Spring 2009 -- DeHon 28 11 2 2 1 1 Collapse at max height Collapsed Node

29. Penn ESE535 Spring 2009 -- DeHon 29 Augmenting Flows Collapsed Node

30. Penn ESE535 Spring 2009 -- DeHon 30 Augmenting Flows Collapsed Node

31. Penn ESE535 Spring 2009 -- DeHon 31 Augmenting Flows Collapsed Node

32. Penn ESE535 Spring 2009 -- DeHon 32 Augmenting Flows Collapsed Node

33. Penn ESE535 Spring 2009 -- DeHon 33 Augmenting Flows Collapsed Node Collapsed Node

34. Penn ESE535 Spring 2009 -- DeHon 34 2 11 2 2 1 1 Collapse at max height Collapsed Node

35. Penn ESE535 Spring 2009 -- DeHon 35 2 11 2 2 1 1 Collapse not work (different/larger graph) Forced to label height+1

36. Penn ESE535 Spring 2009 -- DeHon 36 2 1 1 1 2 1 Reconvergent fanout (yes different graph) Can label at height 1

37. Penn ESE535 Spring 2009 -- DeHon 37 Flowmap Max-flow Min-cut algorithm to find cut Use augmenting paths until discover max flow > K O(K|e|) time to discover K-feasible cut –(or that does not exist) Depth identification: O(KN|e|)

38. Penn ESE535 Spring 2009 -- DeHon 38 2 11 2 2 1 1 Mincut may not be unique Collapsed Node

39. Penn ESE535 Spring 2009 -- DeHon 39 Flowmap Min-cut may not be unique To minimize area achieving delay optimum –find max volume min-cut Compute max flow  find min cut remove edges consumed by max flow DFS from source Compliment set is max volume set

40. Penn ESE535 Spring 2009 -- DeHon 40 Graph

41. Penn ESE535 Spring 2009 -- DeHon 41 Graph: maxflow (K=4)

42. Penn ESE535 Spring 2009 -- DeHon 42 Graph: BFS source Reachable

43. Penn ESE535 Spring 2009 -- DeHon 43 Max Volume min-cut

44. Penn ESE535 Spring 2009 -- DeHon 44 Flowmap Covering from labeling is straightforward –process in reverse topological order –allocate identified K-feasible cut to LUT –remove node –postprocess to minimize LUT count Notes: –replication implicit (covered multiple places) –nodes purely internal to one or more covers may not get their own LUTs

45. Penn ESE535 Spring 2009 -- DeHon 45 Flowmap Roundup Label –Work from inputs to outputs –Find max label of predecessors –Collapse new node with all predecessors at this label –Can find flow cut  K? Yes: mark with label (find max-volume cut extent) No: mark with label+1 Cover –Work from outputs to inputs –Allocate LUT for identified cluster/cover –Recurse covering selection on inputs to identified LUT

46. Penn ESE535 Spring 2009 -- DeHon 46 Area

47. Penn ESE535 Spring 2009 -- DeHon 47 DF-Map Duplication Free Mapping –can find optimal area under this constraint –(but optimal area may not be duplication free) [Cong+Ding, IEEE TR VLSI Sys. V2n2p137]

48. Penn ESE535 Spring 2009 -- DeHon 48 Maximum Fanout Free Cones MFFC: bit more general than trees

49. Penn ESE535 Spring 2009 -- DeHon 49 MFFC Follow cone backward end at node that fans out (has output) outside the code

50. Penn ESE535 Spring 2009 -- DeHon 50 MFFC example

51. Penn ESE535 Spring 2009 -- DeHon 51 MFFC example

52. Penn ESE535 Spring 2009 -- DeHon 52 DF-Map Partition into graph into MFFCs Optimally map each MFFC In dynamic programming –for each node examine each K-feasible cut –note: this is very different than flowmap where only had to examine a single cut pick cut to minimize cost –1 +  MFFCs for fanins

53. Penn ESE535 Spring 2009 -- DeHon 53 DF-Map Example Cones?

54. Penn ESE535 Spring 2009 -- DeHon 54 DF-Map Example

55. Penn ESE535 Spring 2009 -- DeHon 55 DF-Map Example

56. Penn ESE535 Spring 2009 -- DeHon 56 DF-Map Example

57. Penn ESE535 Spring 2009 -- DeHon 57 DF-Map Example

58. Penn ESE535 Spring 2009 -- DeHon 58 DF-Map Example

59. Penn ESE535 Spring 2009 -- DeHon 59 DF-Map Example Start mapping cone

60. Penn ESE535 Spring 2009 -- DeHon 60 DF-Map Example 11 11

61. Penn ESE535 Spring 2009 -- DeHon 61 DF-Map Example ? 11 11

62. Penn ESE535 Spring 2009 -- DeHon 62 DF-Map Example ? 11 11

63. Penn ESE535 Spring 2009 -- DeHon 63 DF-Map Example ? 11 11

64. Penn ESE535 Spring 2009 -- DeHon 64 DF-Map Example 1 11 11

65. Penn ESE535 Spring 2009 -- DeHon 65 DF-Map Example 11 1 1 1 11 Similar to previous

66. Penn ESE535 Spring 2009 -- DeHon 66 DF-Map Example ? 11 1 1 1 11

67. Penn ESE535 Spring 2009 -- DeHon 67 DF-Map Example ? 11 1 1 1 11

68. Penn ESE535 Spring 2009 -- DeHon 68 DF-Map Example ? 11 1 1 1 11 3

69. Penn ESE535 Spring 2009 -- DeHon 69 DF-Map Example ? 11 1 1 1 11

70. Penn ESE535 Spring 2009 -- DeHon 70 DF-Map Example ? 11 1 1 1 11 2

71. Penn ESE535 Spring 2009 -- DeHon 71 DF-Map Example ? 11 1 1 1 11

72. Penn ESE535 Spring 2009 -- DeHon 72 DF-Map Example ? 11 1 1 1 11 3

73. Penn ESE535 Spring 2009 -- DeHon 73 DF-Map Example 2 11 1 1 1 11

74. Penn ESE535 Spring 2009 -- DeHon 74 DF-Map Example 2? 11 1 1 1 11

75. Penn ESE535 Spring 2009 -- DeHon 75 DF-Map Example 2? 11 1 1 1 11

76. Penn ESE535 Spring 2009 -- DeHon 76 DF-Map Example 2? 11 1 1 1 11 3

77. Penn ESE535 Spring 2009 -- DeHon 77 DF-Map Example 2? 11 1 1 1 11 3

78. Penn ESE535 Spring 2009 -- DeHon 78 DF-Map Example 2? 11 1 1 1 11 3 3

79. Penn ESE535 Spring 2009 -- DeHon 79 DF-Map Example 2? 11 1 1 1 11 3 3

80. Penn ESE535 Spring 2009 -- DeHon 80 DF-Map Example 2? 11 1 1 1 11 3 3 3

81. Penn ESE535 Spring 2009 -- DeHon 81 DF-Map Example 23 11 1 1 1 11

82. Penn ESE535 Spring 2009 -- DeHon 82 DF-Map Example 23 11 1 1 ? 1 11

83. Penn ESE535 Spring 2009 -- DeHon 83 DF-Map Example 23 11 1 1 ? 1 11

84. Penn ESE535 Spring 2009 -- DeHon 84 DF-Map Example 23 11 1 1 ? 1 11 4

85. Penn ESE535 Spring 2009 -- DeHon 85 DF-Map Example 23 11 1 1 ? 1 11 4

86. Penn ESE535 Spring 2009 -- DeHon 86 DF-Map Example 23 11 1 1 ? 1 11 4 3

87. Penn ESE535 Spring 2009 -- DeHon 87 DF-Map Example 23 11 1 1 ? 1 11 4 3

88. Penn ESE535 Spring 2009 -- DeHon 88 DF-Map Example 23 11 1 1 ? 1 11 4 3 3

89. Penn ESE535 Spring 2009 -- DeHon 89 DF-Map Example 23 11 1 1 ? 1 11 4 3 3

90. Penn ESE535 Spring 2009 -- DeHon 90 DF-Map Example 23 11 1 1 ? 1 11 4 3 3 4

91. Penn ESE535 Spring 2009 -- DeHon 91 DF-Map Example 23 11 1 1 ? 1 11 4 3 3 4

92. Penn ESE535 Spring 2009 -- DeHon 92 DF-Map Example 23 11 1 1 ? 1 11 4 3 3 4 3

93. Penn ESE535 Spring 2009 -- DeHon 93 DF-Map Example 23 11 1 1 3 1 11

94. Penn ESE535 Spring 2009 -- DeHon 94 DF-Map Example ? 23 11 1 1 3 1 11

95. Penn ESE535 Spring 2009 -- DeHon 95 DF-Map Example ? 23 11 1 1 3 1 11

96. Penn ESE535 Spring 2009 -- DeHon 96 DF-Map Example ? 23 11 1 1 3 1 11 9

97. Penn ESE535 Spring 2009 -- DeHon 97 DF-Map Example ? 23 11 1 1 3 1 11 9 7

98. Penn ESE535 Spring 2009 -- DeHon 98 DF-Map Example ? 23 11 1 1 3 1 11 9 7

99. Penn ESE535 Spring 2009 -- DeHon 99 DF-Map Example ? 23 11 1 1 3 1 11 9 7 5

100. Penn ESE535 Spring 2009 -- DeHon 100 DF-Map Example 5 23 11 1 1 3 1 11

101. Penn ESE535 Spring 2009 -- DeHon 101 DF-Map Example 5 23 11 1 1 3 1 11

102. Penn ESE535 Spring 2009 -- DeHon 102 Composing Don’t need minimum delay off the critical path Don’t always want/need minimum delay Composite: –map with flowmap –Greedy decomposition of “most promising” non-critical nodes –DF-map these nodes

103. Penn ESE535 Spring 2009 -- DeHon 103 Variations on a Theme

104. Penn ESE535 Spring 2009 -- DeHon 104 Applicability to Non-LUTs? E.g. LUT Cascade –can handle some functions of K inputs How apply?

105. Penn ESE535 Spring 2009 -- DeHon 105 Adaptable to Non-LUTs Sketch: –Initial decomposition to nodes that will fit –Find max volume, min-height K-feasible cut –ask if logic block will cover yes  done no  exclude one (or more) nodes from block and repeat –exclude == collapse into start set nodes –this makes heuristic

106. Penn ESE535 Spring 2009 -- DeHon 106 Partitioning? Effectively partitioning logic into clusters –LUT cluster unlimited internal “gate” capacity limited I/O (K) simple delay cost model –1 cross between clusters –0 inside cluster

107. Penn ESE535 Spring 2009 -- DeHon 107 Partitioning Clustering –if strongly I/O limited, same basic idea works for partitioning to components typically: partitioning onto multiple FPGAs assumption: inter-FPGA delay >> intra-FPGA delay –w/ area constraints similar to non-LUT case –make min-cut –will it fit? –Exclude some LUTs and repeat

108. Penn ESE535 Spring 2009 -- DeHon 108 Clustering for Delay W/ no IO constraint area is monotone property DP-label forward with delays –grab up largest labels (greatest delays) until fill cluster size Work backward from outputs creating clusters as needed

109. Penn ESE535 Spring 2009 -- DeHon 109 Area and IO? Real problem: –FPGA/chip partitioning Doing both optimally is NP-hard Heuristic around IO cut first should do well –(e.g. non-LUT slide) –[Yang and Wong, FPGA’94]

110. Penn ESE535 Spring 2009 -- DeHon 110 Partitioning To date: –primarily used for 2-level hierarchy I.e. intra-FPGA, inter-FPGA Open/promising –adapt to multi-level for delay-optimized partitioning/placement on fixed-wire schedule localize critical paths to smallest subtree possible?

111. Penn ESE535 Spring 2009 -- DeHon 111 Summary Optimal LUT mapping NP-hard in general –fanout, replication, …. K-LUTs makes delay optimal feasible –single constraint: IO capacity –technique: max-flow/min-cut Heuristic adaptations of basic idea to capacity constrained problem –promising area for interconnect delay optimization

112. Penn ESE535 Spring 2009 -- DeHon 112 Today’s Big Ideas: IO may be a dominant cost –limiting capacity, delay Exploit structure: K-LUTs Mixing dominant modes –multiple objectives Define optimally solvable subproblem –duplication free mapping