1. 1 Computing with Leakage Currents Nikhil Jayakumar, Kanupriya Gulati, Rajesh Garg and Sunil P. Khatri ECE Department Texas A&M University

2. 2 Outline  Sub-threshold circuits – the opportunity  Challenges  Process/temperature/voltage variations  Energy minimization in sub-threshold circuits  Re-claiming the speed penalty  What’s next?

3. 3 Introduction  Power consumption has become a significant hurdle for recent ICs  Higher power consumption leads to  Shorter battery life  Higher on-chip temperatures – reduced operating life of the chip  There is a large and growing class of applications where power reduction is paramount – not speed.  Such applications are ideal candidates for sub- threshold circuit design.  OK, so what is sub-threshold design??

4. 4  As supply voltage scales down, the V T of the devices is scaled down as well.  A larger V T would reduce leakage but increase delay.  Leakage increases exponentially with decreasing V T  Until a few process generations ago, leakage power was negligible compared to dynamic power  But leakage power is now becoming comparable with dynamic power. Ouch (three times).  Can we turn this dilemma into an opportunity ? Sub-threshold Leakage

5. 5 The Opportunity  Compared traditional circuit with sub-threshold (obtained by simply setting VDD < V T )  Performed simulations for 2 different processes on a 21 stage ring oscillator.  Impressive power reduction (100X – 500X)  Power-Delay-Product (P-D-P) improves by as much as 20X  P-D-P is an important metric to compare circuit design styles  Delay penalty of 10X – 25X can be reduced:  By applying forward body bias (dynamic)  By reducing V T values (static)

6. 6 The Opportunity  We also performed experiments with lower V T values.  V T can be modified with no extra cost  Delays improved, while the PDP improvement remained high.

7. 7 Sub-threshold Logic  Advantages  Circuits get faster at higher temperature. Hence no need for expensive cooling techniques.  Device transconductance is an exponential function of V gs which results in a high ratio of on versus off current. Hence noise margins are near-ideal.  Note that device is never “on”. It is just “off” or “exponentially more off”, so to say  Disadvantages  I ds has an exponential dependence on temperature.  I ds is highly dependent on process variations (such as V T variations).  I ds is small. This explains the delay penalty

8. 8 Solving the Problem of Delay Sensitivity to Process, Voltage and Temperature Variations

9. 9 Our Solution  We propose a technique that uses self-adjusting body-bias to phase-lock the circuit delay to a beat clock.  Use a network of PLAs to implement circuits.  Several PLAs in a cluster share a common Nbulk node.  A representative PLA in each cluster is chosen to phase lock the delay of the PLAs to the beat clock  If the delay is too high, a forward body bias is applied to speed up the PLA.  If the delay is low, the body bias is brought back down to zero to slow down the PLA.

10. 10 PLA structure  We use precharged NOR-NOR PLAs as the structure of choice.  Wordlines run horizontally.  Inputs (and their complements) and the outputs run vertically.  Several PLAs in a cluster share a common Nbulk node.

11. 11 The Charge Pump

12. 12 Effectiveness of the Approach  We simulated a single PLA from 0ºC to 100ºC. Also applied V T variations (10%) and VDD variations (10%).  The light region shows the variations on delay over all the corners.  The red region shows the delays with the self-adjusting body- bias circuit.

13. 13 An Example Showing Phase Locking  This figure shows how the body bias (and hence the delay of the PLA) changes with changes in VDD.  The adjustment is very quick (within a few clock cycles). VDD change 0.2V to 0.22V VDD change 0.22V to 0.18V

14. 14 What about Energy Minimization Minimum Power does not mean Minimum Energy… We are interested in mimimum energy operation given the application scenario envisioned

15. 15 What about Energy ??  Minimizing VDD reduces power.  But minimum VDD does not mean minimum Energy!  There exists an optimum VDD for minimum Energy.

16. 16 Finding the Optimum VDD  While one level of PLAs is Evaluating, the others are Precharged.  The Precharged PLAs are consuming leakage power.  Hence optimum VDD depends on logical depth.

17. 17 The Optimum VDD  The optimum VDD value increases with increased logical depth.  The optimum VDD can vary with temperature (since the circuits get faster with temperature).  The optimum VDD can be estimated given the logical depth and delay for each PLA. 25ºC 100ºC

18. 18 Reclaiming Part of the Speed Penalty

19. 19 Micropipelining Asynchronous Micropipeline.  For high-speed operation, a network of PLAs can be implemented as an Asynchronous Micropipeline.  P1 triggers a precharge event  P2 triggers an evaluate event  Latency increases, but throughput improves dramatically. Handshaking Logic

20. 20 Micropipelining Results  We get an average speedup of 7X over a non- micropipelined design.  After this, sub-threshold circuits are slower by a factor of 1.5X -3.5X over their traditional (non micropipelined) counterparts

21. 21 Layout of the PLA  Each PLA has 16 inputs, 14 outputs and 24 rows (cubes).

22. 22 Ambient Light Powered ICs  The approach lends itself to being powered by energy scavenged from ambient light  Early studies show that this is feasible  New Cadmium Sulfide/Cadmium Telluride solar panels achieve 0.09W/cm 2. (Silicon panels produce 0.015 W/cm 2 )  Estimated power consumption for a subthreshold processor of this size is about 10mW.  So the CdS/CdTe panel could power our processor with a 9X safety margin  Challenges include how to store energy (battery? Supercapacitors? MIM capacitors?).

23. 23 What next?  Explore extensions to structured ASIC approaches  Fabrication of a subthreshold design (in 2006)  Mixed-signal – with small processor and transceiver on a single die.  Set up a small hardware lab for debug/diagnosis  Validate the experiments we discussed  Hope to use this test-chip to validate other ideas as well.  Develop a design methodology for sub- threshold electronics, tuned for widespread use.

24. 24 Summary  Sub-threshold circuit design is promising due to extreme low power.  The delay phase locking approach helps sub-threshold logic design overcome the hurdle of sensitivity to PVT variations.  This can help achieve a significant yield improvement.  The study on optimum VDD for minimum Energy helps to fix an optimum VDD for a given logical depth.  Micro-pipelining helps bridge the delay gap.  Sub-threshold design approaches are appealing for a widening class of low power or energy applications.  Goal : Help bring sub-threshold logic design into the mainstream of VLSI technology.

25. 25 Thank you!!