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Registers and Shift Registers Discussion D8.2
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D Flip-Flop 0 0 1 1 1 0 X 0 Q 0 ~Q 0 D CLK Q ~Q D gets latched to Q on the rising edge of the clock. Positive edge triggered
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A 1-Bit Register
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If LOAD = 1, then INP0 gets latched to Q0 on the rising edge of the clock, CLK
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A 4-Bit Register
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Implementing Registers in Verilog //A 4-bit register with asynchronous clear and load module reg4(Clk,Clear,Load,D,Q); input [3:0] D; input Clk,Clear,Load; output [3:0] Q; reg [3:0] Q; always @(posedge Clk or posedge Clear) if(Clear == 1) Q <= 0; else if(Load) Q <= D; endmodule
![Implementing Registers in Verilog //A 4-bit register with asynchronous clear and load module reg4(Clk,Clear,Load,D,Q); input [3:0] D; input Clk,Clear,Load; output [3:0] Q; reg [3:0] Q; Clk or posedge Clear) if(Clear == 1) Q <= 0; else if(Load) Q <= D; endmodule](http://images.slideplayer.com./17/5328517/slides/slide_6.jpg "Implementing Registers in Verilog //A 4-bit register with asynchronous clear and load module reg4(Clk,Clear,Load,D,Q); input [3:0] D; input Clk,Clear,Load; output [3:0] Q; reg [3:0] Q; Clk or posedge Clear) if(Clear == 1) Q <= 0; else if(Load) Q <= D; endmodule")
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4-Bit Shift Register
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shift4.v module ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= data_in; Q[2:0] <= Q[3:1]; end endmodule Note non-blocking assignment
![shift4.v module ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= data_in; Q[2:0] <= Q[3:1]; end endmodule Note non-blocking assignment](http://images.slideplayer.com./17/5328517/slides/slide_8.jpg "shift4.v module ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q; reg [3:0] Q; // 4-bit Shift Register clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= data_in; Q[2:0] <= Q[3:1]; end endmodule Note non-blocking assignment")
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shift4 simulation
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Ring Counter
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ring4.v module ring4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Ring Counter always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1]; end endmodule
![ring4.v module ring4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Ring Counter clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1]; end endmodule](http://images.slideplayer.com./17/5328517/slides/slide_11.jpg "ring4.v module ring4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Ring Counter clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1]; end endmodule")
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ring4 simulation
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Johnson Counter
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module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Johnson Counter always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1]; end endmodule johnson4.v
![module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Johnson Counter clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1]; end endmodule johnson4.v](http://images.slideplayer.com./17/5328517/slides/slide_14.jpg "module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Johnson Counter clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1]; end endmodule johnson4.v")
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Johnson Counter
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A Random Number Generator
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Q3 Q2 Q1 Q0 0 0 0 1 1 1 0 0 0 8 1 1 0 0 C 1 1 1 0 E 1 1 1 1 F 0 1 1 1 7 1 0 1 1 B 0 1 0 1 5 Q3 Q2 Q1 Q0 1 0 1 0 A 1 1 0 1 D 0 1 1 0 6 0 0 1 1 3 1 0 0 1 9 0 1 0 0 4 0 0 1 0 2 0 0 0 1 1
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module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Random number generator always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1]; end endmodule rand4.v
![module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Random number generator clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1]; end endmodule rand4.v](http://images.slideplayer.com./17/5328517/slides/slide_18.jpg "module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q; reg [3:0] Q; // 4-bit Random number generator clk or posedge clr) begin if(clr == 1) Q <= 1; else begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1]; end endmodule rand4.v")
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A Random Number Generator
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clk inp Q2 Q0 Q1 outp Clock Pulse
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module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp; wire outp; reg [2:0] Q; // clock pulse generator always @(posedge clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[2] <= inp; Q[1:0] <= Q[2:1]; end assign outp = Q[2] & Q[1] & ~Q[0]; endmodule clk_pulse.v
![module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp; wire outp; reg [2:0] Q; // clock pulse generator clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[2] <= inp; Q[1:0] <= Q[2:1]; end assign outp = Q[2] & Q[1] & ~Q[0]; endmodule clk_pulse.v](http://images.slideplayer.com./17/5328517/slides/slide_21.jpg "module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp; wire outp; reg [2:0] Q; // clock pulse generator clk or posedge clr) begin if(clr == 1) Q <= 0; else begin Q[2] <= inp; Q[1:0] <= Q[2:1]; end assign outp = Q[2] & Q[1] & ~Q[0]; endmodule clk_pulse.v")
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clk inp Q2 Q0 Q1 outp
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