1. RLC Interconnect Modeling and Design Students: Jinjun Xiong, Jun Chen Advisor: Lei He Electrical Engineering Department Design Automation Group (http://eda.ee.ucla.edu) University of California at Los Angeles, Los Angeles, CA, 90095 Sponsors: Analog Devices, Intel, NSF, Synopsis Abstract Signal integrity becomes one of primary design constraints as the clock frequency increases and minimum feature size continues to shrink. State-of-the-art noise avoidance techniques use only a capacitive model. However, inductive coupling gains growing importance for GHz+ VLSI design. We present the following for RLC interconnect modeling and design: (1) RLC noise modeling at both tile and full-chip levels; and (2) tile-based interconnect synthesis and chip-level post-routing optimization, both under RLC noise constraints. WCN Algorithm Pseudo Exhaustive Searching(PES) Simultaneously Switching(SS) –All aggressors switching simultaneously Superposition(SP) –Sum of individual noise amplitudes of all aggressors. Aligned Switching(AS) –Example of two aggressors Experiment Results Aligning tt Settings: six-bit bus structure with two shields RC model severely underestimates WCN SP can underestimate WCN up to 24% –SP was believed an upper bound of WCN SS+AS is a good approximation of PES, the best WCN algorithm –SS+AS has linear complexity –PES has exponential complexity Post Routing Optimization Simultaneous shield insertion and net ordering (SINO): –Given: a set of net segments and their noise bounds at one tile. –Find: a min-area SINO solution. –Such that all net segments are capacitive noise free and have inductive noise less than the given bounds. Keff Model Inductive Coupling coefficient: K(i,j) can be approximated by: Keff model approximates WCN in SINO structures by weighted sum of K(i,j): –S(i,j): sensitivity between N i and N j Keff model has high fidelity for RLC WCN in SINO structures, but is orders of magnitude faster. SINO Algorithm SINO is NP-hard Simulated annealing leads to high-quality solution in short runtime Up to 20% total routing area reduction over uniform shield insertion without net ordering Shielding Estimation Shielding estimation facilitates –Early physical design decision-making –Routing optimization Estimated number of shields is: A multi-variable regression method is used to fit the number of shields. IIIIIIIVV  a1 -0.10956-0.10408-0.09781-0.10605-0.107950.0045 a2 0.503390.475150.470250.494200.515000.0188 R ^2 0.81860.80710.84190.87110.89720.0372 –Randomly generate 10,000 routing solutions –Evenly divide the the SINO solution in 5 groups –The small standard deviation (  ) values imply the convergence of the parameters and the goodness of the shield estimation equation. Interconnect Synthesis Given: –A global routing solution. –The RLC crosstalk bound at each sink. Find: –The coupling bound for each net segment. –A min-area SINO solution within each tile. Such that: –RLC crosstalk bound is satisfied at each sink. –The routing area is minimized. LSK Model Noise is nearly proportional to the length in SINO solutions. For each sink, LSK value is –Sum over the path from source to sink; –L t : length of the tile t where net i is routed; –K it : the total inductive coupling of N i under Keff model Multiple Phase Algorithm Given a global routing solution and the RLC crosstalk bound at each sink –Phase I: Crosstalk budgeting at the full-chip level. –Phase II: SINO within each region. –Phase III: Local refinement.  Eliminate remaining but very limited RLC crosstalk violations.  Reduce routing congestion and further reduce over-design. Phase I partitions crosstalk bounds among all routing regions such that the weighted sum of height and width is minimized, and is a linear programming (LP) problem. S.t. Experiment Results 123456789 Sens Rate Budget Scheme Phase IPhase IIPhase IIILSK Bound (1000) Shieldhmax+wmaxShieldhmax+wmaxShieldhmax+wmax Primary1 (16x16) 50%UD261.0193.6+194.8258194+194129188+192995.5/269.9 LP688.9190.7+194.8 (-0.75%) 378182+191 (-3.87%) 170182+185 (-3.42%) 997.5/266.5 70%UD368.5199.2+199.1395200+199228191+193998.4/310.8 LP879.0190.6+193.3 (-3.62%) 692182+196 (-5.26%) 406183+187 (-3.65%) 999.0/272.5 All max/avg LSK values meet the bound (1000); No crosstalk violations! As sensitivity rate/obstacle increases, the routing area increases, and so does the number of shields. Even though LP consumes more shields, the area is not necessary larger –Compared to best alternative with uniform budgeting (UD) in Phase I. Reference K.Lepak, et al., “Shield insertion and net ordering under explicit RLC noise constraint”, DAC 01. J. Xiong, et al., “Post global routing RLC crosstalk budgeting”, ICCAD 02. L. He and M. Xu, “Modeling and Layout Optimization for On-chip Inductive Coupling”, UW-Madison Tech. Report 00. J. Chen and L. He, “Determination of worst-case crosstalk noise for non-switching victims in GHz+ Interconnects”, TAU 02. WCN Problem Formulation Worst Case Noise Problem (WCN) –Given an interconnect structure and multiple aggressors, find the maximum noise amplitude on the specified victim. WCN under RC depends on aggressor switching time only. WCN under RLC depends on both aggressor switching time and aggressor switching pattern. SS+AS –Combining SS and AS