1. LCD Display DIO2 Board CPLD

2. DIO2 Board CPLD Interface LCD Display

3. DIO2 circuit board block diagram

4. Top Level Design

5. library IEEE; use IEEE.STD_LOGIC_1164.all; entity buff3 is generic (width:positive); port( input : in STD_LOGIC_vector(width-1 downto 0); en : in STD_LOGIC; output : out STD_LOGIC_vector(width-1 downto 0) ); end buff3; architecture buff3 of buff3 is begin output 'Z'); end buff3; buff3.vhd en output input

6. DIO2 CPLD VHDL Code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity d2io is Port ( btns : in std_logic_vector(14 downto 0); switchs : in std_logic_vector(7 downto 0); leds : out std_logic_vector(15 downto 0); data : inout std_logic_vector(7 downto 0); addr : in std_logic_vector(5 downto 0); sseg : out std_logic_vector(6 downto 0); ssegdp : out std_logic; ssegsel : out std_logic_vector(3 downto 0); cs : in std_logic; we : in std_logic; oe : in std_logic; clk256 : in std_logic); end d2io;

7. architecture rtl of d2io is signal data_out : std_logic_vector(7 downto 0); signal sseg_reg : std_logic_vector(15 downto 0); signal digit : std_logic_vector(3 downto 0); signal count : unsigned(1 downto 0); signal leds_i : std_logic_vector(15 downto 0); signal strobe : std_logic; begin ssegdp <= '1'; data <= data_out when (oe = '1' and cs = '1') else (others => 'Z'); data_out <= btns(7 downto 0) when addr(1 downto 0) = "00" else '0'& btns(14 downto 8) when addr(1 downto 0) = "01" else switchs;

8. strobe <= cs and we; leds <= not(leds_i); process(strobe) begin if(falling_edge(strobe)) then case addr is when "000100" => leds_i(7 downto 0) <= data; when "000101" => leds_i(15 downto 8) <= data; when "000110" => sseg_reg(15 downto 8) <= data; when "000111" => sseg_reg(7 downto 0) <= data; when others => NULL; end case; end if; end process;

9. process(clk256) begin if(rising_edge(clk256)) then count <= count + 1; end if; end process; with count select digit <= sseg_reg(7 downto 4) when "00", sseg_reg(3 downto 0) when "01", sseg_reg(15 downto 12) when "10", sseg_reg(11 downto 8) when others; process(count) begin ssegsel '0'); ssegsel(conv_integer(count)) <= '1'; end process;

10. with digit select sseg <="1001111" when "0001",--1 "0010010" when "0010",--2 "0000110" when "0011",--3 "1001100" when "0100",--4 "0100100" when "0101",--5 "0100000" when "0110",--6 "0001111" when "0111",--7 "0000000" when "1000",--8 "0000100" when "1001",--9 "0001000" when "1010",--A "1100000" when "1011",--b "0110001" when "1100",--C "1000010" when "1101",--d "0110000" when "1110",--E "0111000" when "1111",--F "0000001" when others;--0 end rtl;

11. DIO2 Board CPLD Interface LCD Display

12. DIO2 circuit board block diagram

17. when LCDistore => LCD_RW <= '0'; LCD_RS <= '0'; pinc <= '0'; if ccycle < 7 then LCD_E <= '1'; else tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; end if; when LCDdstore => LCD_RW <= '0'; LCD_RS <= '1'; pinc <= '0'; if ccycle < 7 then LCD_E <= '1'; else tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; dpop <= '1'; end if; In wc16_control add…. LCDinst! ( data 0.. ) LCDdata! ( data 0.. )

18. Lcd3.whp \ LCD for Digilab DIO2 \ LCD3.WHP HEX : 1ms_Delay( -- ) 30D1 FOR NEXT ; : 30ms.Delay ( -- ) 1E FOR 1ms_Delay NEXT ; : hex2asc ( n -- asc ) 0F AND \ mask upper nibble DUP 9 > \ if n > 9 IF 37 + \ add $37 ELSE 30 + \ else add $30 THEN ;

19. Lcd3.whp : lcd.init ( -- ) 30ms.delay 3C 0 LCDinst! \ 2 x 40 display 1ms_Delay 0f 0 LCDinst! \ display on 1ms_Delay 1 0 LCDinst! \ display clear 1ms_Delay 1ms_Delay 6 0 LCDinst! \ entry cursor shift off 1ms_Delay ;

21. : hex>lcd ( hex -- ) HEX2ASC 0 LCDdata! 30ms.delay; : u.lcd ( u -- )\display T on LCD DUP C RSHIFT hex>lcd DUP 8 RSHIFT hex>lcd DUP 4 RSHIFT hex>lcd hex>lcd ; Lcd3.whp

22. : MAIN ( -- ) lcd.init BEGIN waitB4 S@\ get high byte DUP DIG! DUP hex>lcd 8 LSHIFT waitB4 S@\ get low byte OR DUP DIG! DUP hex>lcd waitB4 u.lcd \ display on lcd AGAIN ; Lcd3.whp