1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 313 - Computer Organization Multi-Cycle Processor Design 1 Feb 2005 Reading: 5.5 Portions of these slides are derived from: Textbook figures © 1998 Morgan Kaufmann Publishers all rights reserved Tod Amon's COD2e Slides © 1998 Morgan Kaufmann Publishers all rights reserved Dave Patterson’s CS 152 Slides - Fall 1997 © UCB Rob Rutenbar’s 18-347 Slides - Fall 1999 CMU other sources as noted

2. Feb 2005Multicycle Design 12 Outline - Multicycle Design  Overview   Datapath Design  Controller Design  Microprogramming  Exceptions  Performance Considerations

3. Feb 2005Multicycle Design 13 Multicycle Execution - Key Idea  Break instruction execution into multiple cycles  One clock cycle for each major task 1.Instruction Fetch 2.Instruction Decode and Register Fetch 3.Execution, memory address computation, or branch computation 4.Memory access / R-type instruction completion 5.Memory read completion  Share hardware to simplify datapath

4. Feb 2005Multicycle Design 14 Characteristics of Multicycle Design  Instructions take more than one cycle  Some instructions take more cycles than others  Clock cycle is shorter than single-cycle clock  Reuse of major components simplifies datapath  Single ALU for all calculations  Single memory for instructions and data  But, added registers needed to store values across cycles  Control Unit Implemented w/ State Machine  Control signals no longer a function of just the instruction

5. Feb 2005Multicycle Design 15 Outline - Multicycle Design  Overview  Datapath Design   Controller Design  Microprogramming  Exceptions  Performance Considerations

6. Feb 2005Multicycle Design 16 Multicycle Datapath - High-Level View (Equivalent to Book Fig. 5.25, p. 318) Additional registers

7. Feb 2005Multicycle Design 17 Review: Steps in Processor Design 1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals

8. Feb 2005Multicycle Design 18 Review: Register Transfers  Instruction Fetch Instruction <- MEM[PC]; PC = PC + 4;  Instruction Execution Instr.Register Transfers add R[rd] <- R[rs] + R[rt]; sub R[rd] <- R[rs] - R[rt]; and R[rd] <- R[rs] & R[rt]; or R[rd] <- R[rs] | R[rt]; lw R[rt] <- MEM[R[rs] + s_extend(offset)]; sw MEM[R[rs] + sign_extend(offset)] <- R[rt];PC <- PC + 4 beq if (R[rs] == R[rt]) then PC <- PC+4 + s_extend(offset<<2) else PC <- PC + 4 j PC <- upper(PC)@(address << 2) Key idea: break into multiple cycles!

9. Feb 2005Multicycle Design 19 Multicycle Execution Steps 1.Instruction Fetch 2.Instruction Decode and Register Fetch (and branch target calculation) 3.One of the following:  Execute R-Type Instruction OR  Calculate memory address for load/store OR  Perform comparison for branch 4.Memory access for load/store OR R-type instruction completion (save result) 5.Memory read completion (save result - load only)

10. Feb 2005Multicycle Design 110 Summary - Multicycle Execution  Instructions take between 3 and 5 clock cycles (Book Fig. 5.30, p. 329) (1) (2) (3) (4) (5) New registers needed to store values across clock steps! Step name Action for R-type instructions Action for memory-reference instructions Action for branches Action for jumps Instruction fetch IR = Memory[PC] PC = PC + 4 Instruction A = Reg [IR[25-21]] decode/register fetch B = Reg [IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) Execution, addressALUOut = A op B ALUOut = A + sign-extendif (A ==B) thenPC = PC [31-28] II computation, branch/ (IR[15-0])PC = ALUOut(IR[25-0]<<2) jump completion Memory access or Reg [IR[15-11]] = Load: MDR = Memory[ALUOut] R-type completion ALUOutor Store: Memory [ALUOut] = B Memory read completion Load: Reg[IR[20-16]] = MDR

11. Feb 2005Multicycle Design 111 Multicycle Execution Step (1) Instruction Fetch IR = Memory[PC]; PC = PC + 4; 4 PC + 4

12. Feb 2005Multicycle Design 112 Multicycle Execution Step (2) Instruction Decode and Register Fetch A = Reg[IR[25-21]];(A = Reg[rs]) B = Reg[IR[20-15]];(B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) Branch Target Address Reg[rs] Reg[rt] PC + 4

13. Feb 2005Multicycle Design 113 Multicycle Execution Steps (3) Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); Mem. Address Reg[rs] Reg[rt] PC + 4

14. Feb 2005Multicycle Design 114 Multicycle Execution Steps (3) ALU Instruction (R-Type) ALUOut = A op B R-Type Result Reg[rs] Reg[rt] PC + 4

15. Feb 2005Multicycle Design 115 Multicycle Execution Steps (3) Branch Instructions if (A == B) PC = ALUOut; Branch Target Address Reg[rs] Reg[rt] Branch Target Address

16. Feb 2005Multicycle Design 116 Multicycle Execution Step (3) Jump Instruction PC = PC[31-28] concat (IR[25-0] << 2) Jump Address Reg[rs] Reg[rt] Branch Target Address

17. Feb 2005Multicycle Design 117 Multicycle Execution Steps (4) Memory Access - Read (lw) MDR = Memory[ALUOut]; Mem. Data PC + 4 Reg[rs] Reg[rt] Mem. Address

18. Feb 2005Multicycle Design 118 Multicycle Execution Steps (4) Memory Access - Write (sw) Memory[ALUOut] = B; PC + 4 Reg[rs] Reg[rt]

19. Feb 2005Multicycle Design 119 Multicycle Execution Steps (4) ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOUT R-Type Result Reg[rs] Reg[rt] PC + 4

20. Feb 2005Multicycle Design 120 Multicycle Execution Steps (5) Memory Read Completion (lw) Reg[IR[20-16]] = MDR; PC + 4 Reg[rs] Reg[rt] Mem. Data Mem. Address

21. Feb 2005Multicycle Design 121 Summary - Multicycle Execution  Instructions take between 3 and 5 clock cycles (Book Fig. 5.30, p. 329)

22. Feb 2005Multicycle Design 122 Full Multicycle Datapath (Equivalent to Book Fig. 5.27, p. 322 without ALU control)

23. Feb 2005Multicycle Design 123 Full Multicycle Implementation (Equivalent to Book Fig. 5.28, p. 323)

24. Feb 2005Multicycle Design 124 Outline - Multicycle Design  Overview  Datapath Design  Controller Design   Performance Considerations  Microprogramming  Exceptions

25. Feb 2005Multicycle Design 125 Review: Steps in Processor Design 1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals

26. Feb 2005Multicycle Design 126 Multicycle Execution Step (1) Fetch IR = Memory[PC]; PC = PC + 4; 1 0 1 0 1 0 X 0 X 0 010 1 55 RD1 RD2 RN1RN2WN WD RegWrite Registers Operation ALU 3 E X T N D 1632 Zero RD WD MemRead Memory ADDR MemWrite 5 Instruction I 32 ALUSrcB <<2 PC 4 RegDst 5 I R M D R M U X 0 1 2 3 M U X 1 0 M U X 0 1 A B ALU OUT 0 1 2 M U X <<2 CONCAT 2832 M U X 0 1 ALUSrcA jmpaddr I[25:0] rd MUX 01 rtrs immediate PCSource MemtoReg IorD PCWr* IRWrite

27. Feb 2005Multicycle Design 127 Multicycle Execution Step (2) Instruction Decode and Register Fetch A = Reg[IR[25-21]];(A = Reg[rs]) B = Reg[IR[20-15]];(B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) 0 0 X 0 0 X 3 0 X X 010 0

28. Feb 2005Multicycle Design 128 0 X Multicycle Execution Steps (3) Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); X 2 0 0 X 0 1 X 010 0

29. Feb 2005Multicycle Design 129 Multicycle Execution Steps (3) ALU Instruction (R-Type) ALUOut = A op B 0 X X 0 0 0 X 0 1 X ??? 0

30. Feb 2005Multicycle Design 130 1 if Zero=1 Multicycle Execution Steps (3) Branch Instructions if (A == B) PC = ALUOut; 0 X X 0 0 X 0 1 1 011 0

31. Feb 2005Multicycle Design 131 Multicycle Execution Step (3) Jump Instruction PC = PC[21-28] concat (IR[25-0] << 2) 0 X X X 0 1 X 0 X 2 XXX 0

32. Feb 2005Multicycle Design 132 Multicycle Execution Steps (4) Memory Access - Read (lw) MDR = Memory[ALUOut]; 0 X X X 1 0 1 0 X X XXX 0

33. Feb 2005Multicycle Design 133 Multicycle Execution Steps (4) Memory Access - Write (sw) Memory[ALUOut] = B; 0 X X X 0 0 1 1 X X XXX 0

34. Feb 2005Multicycle Design 134 1 0 0 X 0 X 0 XXX X X 1 1 Multicycle Execution Step (4) ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOut;(Reg[Rd] = ALUOut)

35. Feb 2005Multicycle Design 135 Multicycle Execution Steps (5) Memory Read Completion (lw) Reg[IR[20-16]] = MDR; 1 0 0 X 0 0 X 0 X X XXX 0 1

36. Feb 2005Multicycle Design 136 Review: Steps in Processor Design 1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals

37. Feb 2005Multicycle Design 137 Full Multicycle Implementation

38. Feb 2005Multicycle Design 138 Multicycle Control Unit  Review: single-cycle implementation  All control signals can be determined by current instruction + condition  Implemented in combinational logic  Multicycle implementation is different  Control signals depend on current instruction which clock cycle is currently being executed  Implemented as Finite State Machine (FSM) OR Microprogrammed Implementation - “stylized FSM”

39. Feb 2005Multicycle Design 139 Review - Finite State Machines  What’s in the Finite State Machine  Combinational Logic  Storage Elements (Flip-flops) Inputs Outputs Current State Next State stored in storage elements

40. Feb 2005Multicycle Design 140 Review - Finite State Machines (cont’d)  Behavior characterized by  States - unique values of flip-flops e.g., “101”  Transitions between states, depending on current state inputs  Output values, depending on current state inputs  Describing FSMs:  State Diagrams  State Transition Tables

41. Feb 2005Multicycle Design 141 Review - State Diagrams  "Bubbles" - states  Arrows - transition edges labeled with condition expressions  Example: Car Alarm arm door honk clk f clk = 1Hz IDLE BEEP Honk=1 WAIT ARMDOOR ARM ARM’ ARM’ + ARMDOOR’ = ARM’ + DOOR’ ARM’

42. Feb 2005Multicycle Design 142 State Transition Table  Transition List - lists edges in State Diagram PSConditionNSOutput IDLEARM' + DOOR'IDLE0 IDLEARM*DOORBEEP0 BEEPARMWAIT1 BEEPARM'IDLE1 WAITARMBEEP0 WAITARM'IDLE0 IDLE BEEP Honk=1 WAIT ARMDOOR ARM ARM’ ARM’ + ARMDOOR’ = ARM’ + DOOR’ ARM’

43. Feb 2005Multicycle Design 143 State Machine Design  Traditional Approach:  Create State Diagram  Create State Transition Table  Assign State Codes  Write Excitation Equations & Minimize  Modern Approach  Enter FSM Description into CAD program  Synthesize implementation of FSM

44. Feb 2005Multicycle Design 144 FSM Control Unit Implementation  FSM Inputs:  Clock  Instruction register op field  FSM Outputs: control signals for datapath  Enable signals: Register file, Memory, PC, MDR, and IR  Multiplexer signals: ALUSrcA, ALUSrcB, etc.  ALUOp signal - used for ALU Control as in single-cycle implementation

45. Feb 2005Multicycle Design 145 Describing Controller Function in State Diagrams - Conventions  Enable Control Signals  Asserted (true) in a state if they appear in the state bubble  Assumed Deasserted (false) in a state if they do not appear in the state bubble  Multiplexer/ALU Control Signals  Asserted with a given value in a state if they appear in a state bubble  Assumed Don’t Care if they do not appear in the state bubble  See Figures 5.32 - 5.36 3 MemRead IorD = 0 Memory access (Op=‘LW’) Enable signal Multiplexer signal State name Transition from previous state (conditioanl) Transition to next state (unconditioanl)

46. Feb 2005Multicycle Design 146 Multicycle Control - Full State Diagram 0 Instruction Fetch Instruction decode / register fetch 1 2 Memory address computation 3 4 57 689 Execution Branch Completion Jump Completion Memory access Memory access R-type completion Writeback step Start MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 (OP = ‘LW’) (OP = (‘SW’) MemRead IorD = 1 RegWrite MemToReg=1 RegDst = 0 MemWrite IorD = 1 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RegDst = 1 RegWrite MemtoReg = 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01 PCWrite PCSource = 10 Op=LW or SW Op=R-type Op=BEQ Op=J

47. Feb 2005Multicycle Design 147 State 8 Branch State (OP = ‘BEQ’) State 6 Execution States (OP = ‘R-Type’) State 2 Mem. Ref States (Op = ‘LW’ or Op = ‘SW’) Control FSM - Instruction Fetch / Decode States MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 State 0 Instruction Fetch Start State 1 Instruction Decode / Register Fetch State 9 Jump State (OP = ‘J’) ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00

48. Feb 2005Multicycle Design 148 Control FSM - Memory Reference States (OP = ‘LW’) State 3 Memory Access State 4 Write-back step State 5 Memory Access (OP = ‘SW’) Memory Address ComputationState 2 from State 1 (OP = ‘LW’ OR OP = ‘SW’) to State 0 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 MemRead IorD = 1 MemWrite IorD = 1 RegWrite MemToReg=1 RegDst = 0

49. Feb 2005Multicycle Design 149 Control FSM - R-Type States State 7 R-type completion to State 0 State 6 from State 1 (OP = R-Type) Execution ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RegDst = 1 RegWrite MemtoReg = 0

50. Feb 2005Multicycle Design 150 Control FSM - Branch State State 8 Branch Completion from State 1 (OP = ‘BEQ’) to State 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01

51. Feb 2005Multicycle Design 151 Control FSM - Jump State State 9 Jump Completion from State 1 (OP = ‘J’) to State 0 PCWrite PCSource = 10

52. Feb 2005Multicycle Design 152 Coming Up  Multicycle Implementation Performance  Multicycle Controller Implementation  Microprogrammed Control  Exceptions