1. Spring 2002EECS150 - Lec10-cl1 Page 1 EECS150 - Digital Design Lecture 10 - Combinational Logic Circuits Part 1 Feburary 26, 2002 John Wawrzynek

2. Spring 2002EECS150 - Lec10-cl1 Page 2 Combinational Logic (CL) Defined y i = f i (x0,...., xn-1), where x, y are {0,1}. Y is a function of only X. If we change X, Y will change immediately (well almost!). There is an implementation dependent delay from X to Y.

3. Spring 2002EECS150 - Lec10-cl1 Page 3 Adders Full-adder cell (FA) revisited:

4. Spring 2002EECS150 - Lec10-cl1 Page 4 Carry-ripple Adder Each cell: r i = a i XOR b i XOR c in c out = a i c in + a i b i + b i c in = c in (a i + b i ) + a i b i 4-bit adder: What about subtraction? “Full adder cell”

5. Spring 2002EECS150 - Lec10-cl1 Page 5 Subtractors A - B = A + (-B) How do we form -B? 1. complement B 2. add 1

6. Spring 2002EECS150 - Lec10-cl1 Page 6 Adders (cont.) Ripple Adder Ripple adder is inherently slow because, in general s7 must wait for c7 which must wait for c6 … T  n, Cost  n How do we make it faster, perhaps with more cost?

7. Spring 2002EECS150 - Lec10-cl1 Page 7 Carry Select Adder T = T ripple_adder / 2 + T MUX COST = 1.5 * COST ripple_adder + (n+1) * COST MUX

8. Spring 2002EECS150 - Lec10-cl1 Page 8 Carry Select Adder Extending Carry-select to multiple blocks What is the optimal # of blocks and # of bits/block? –If # blocks too large delay dominated by total mux delay –If # blocks too small delay dominated by adder delay T  sqrt(N), Cost  2*ripple + muxes

9. Spring 2002EECS150 - Lec10-cl1 Page 9 Carry Select Adder T total = sqrt(N) T FA –assuming T FA = T MUX For ripple adder T total = N T FA Is sqrt(N) really the optimum? –From right to left increase size of each block to better match delays –Ex: 64-bit adder, use block sizes [13 12 11 10 9 8 7] How about recursively defined carry select?

10. Spring 2002EECS150 - Lec10-cl1 Page 10 Carry Look-ahead Adders In general, for n-bit addition best we can achieve is delay  log(n) How do we arrange this? (think trees) First, reformulate basic adder stage: carry “kill” k i = a i ’ b i ’ carry “propagate” p i = a i  b i carry “generate” g i = a i b i c i+1 = g i + p i c i s i = p i  c i a b c i c i+1 s

11. Spring 2002EECS150 - Lec10-cl1 Page 11 Carry Look-ahead Adders Ripple adder using p and g signals: So far, no advantage over ripple adder: T  N p0p0 g0g0 s 0 = p 0  c 0 c 1 = g 0 + p 0 c 0 s0s0 a0a0 b0b0 p1p1 g1g1 s 0 = p 1  c 1 c 2 = g 1 + p 1 c 1 s1s1 a1a1 b1b1 p2p2 g2g2 s 2 = p 2  c 2 c 3 = g 2 + p 2 c 2 s2s2 a2a2 b2b2 p3p3 g3g3 s 3 = p 3  c 3 c 4 = g 3 + p 3 c 3 s3s3 a3a3 b3b3 c0c0 c4c4

12. Spring 2002EECS150 - Lec10-cl1 Page 12 Carry Look-ahead Adders Expand carries: c 0 c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 g 0 + p 1 p 0 c 0 c 3 = g 2 + p 2 c 2 = g 2 + p 2 g 1 + p 1 p 2 g 0 + p 2 p 1 p 0 c 0 c 4 = g 3 + p 3 c 3 = g 3 + p 3 g 2 + p 3 p 2 g 1 +.... Why not implement these equations directly to avoid ripple delay? –Lots of gates. Redundancies (full tree for each). –Gate with high # of inputs. Let’s reorganize the equations.

13. Spring 2002EECS150 - Lec10-cl1 Page 13 Carry Look-ahead Adders “Group” propagate and generate signals: P true if the group as a whole propagates a carry to c out G true if the group as a whole generates a carry Group P and G can be generated hierarchically. pipi gigi p i+1 g i+1 p i+k g i+k P = p i p i+1 … p i+k G = g i+k + p i+k g i+k-1 + … + (p i+1 p i+2 … p i+k )g i c in c out C out = G + PC in

14. Spring 2002EECS150 - Lec10-cl1 Page 14 Carry Look-ahead Adders a0a0 b0b0 a1a1 b1b1 a2a2 b2b2 a a3a3 b3b3 a4a4 b4b4 a5a5 b5b5 b c 3 = G a + P a c 0 PaPa GaGa PbPb GbGb a6a6 b6b6 a7a7 b7b7 a8a8 b8b8 c c 6 = G b + P b c 3 PcPc GcGc P = P a P b P c G = G c + P c G b + P b P c G a c 9 = G + Pc 0 c0c0 9-bit Example of hierarchically generated P and G signals:

15. Spring 2002EECS150 - Lec10-cl1 Page 15 p0p0 g0g0 s0s0 p1p1 g1g1 s1s1 c 1 = g 0 +p 0 c 0 p1p1 g2g2 s2s2 c2c2 p3p3 g3g3 s3s3 c 3 = g 2 +p 2 c 2 p4p4 g4g4 s4s4 p5p5 g5g5 s5s5 p6p6 g6g6 s6s6 c6c6 p7p7 g7g7 s7s7 c0c0 c 5 = g 4 +p 4 c 4 c 7 = g 6 +p 6 c 6 c4c4 c 2 =G 8 +P 8 c 0 P 8 =p 0 p 1 G 8 =g 1 +p 1 g 0 P 9 =p 2 p 3 c 6 =G a +P a c 4 P a =p 4 p 5 G a =g 5 +p 5 g 4 P b =p 6 p 7 G 9 =g 3 +p 3 g 2 G b =g 7 +p 7 g 6 c 4 =G c +P c c 0 P c =P 8 P 9 G c =G 9 +P 9 G 8 P d =P a P b G d =G b +P b G a c 8 =G e +P e c 0 P e =P c P d G e =G d +P d G c c0c0 c4c4 c8c8 8-bit Carry Look-ahead Adder with 2-input gates.

16. Spring 2002EECS150 - Lec10-cl1 Page 16 Adders in FPGAs