1. User Programmable Logic Device: Architecture and CAD Tools TingTing Hwang and C. L. Liu

2. Design Decisions Mid-size Capacity For control logic Hierarchical Interconnection Structure Predictable delay PLA-based Cell Structure

3. New Architecture Cell Structure Interconnection Architecture

4. Single-Output PLA Cells Investigate the tradeoff between chip area/delay and cell granularity for single-output PLA cells.

5. Conclusions for Cell Structure Area model: 3-4 inputs, 2 products PLA-based FPGA area versus cell granularity by Kouloheris and Gamal: 8-10 inputs, 12-13 products, 3-4 outputs Area model plays an important role in the architecture evaluation process

6. Interconnect Architecture 2 2 2 2 2 4 4 2 2 2 A B 2 2 A B 2 2 2 PI=6 level2 A B level3level4 PO=6 4 2 S=2 level1 12 1234

7. PI switch logic cell Hierarchical Interconnect Structure

8. Graph Model of Interconnections pin1pin2 PI cell3 input Level3_input Level2_input Level1_input cell1cell2 output

9. Development Flow Input Technology Mapping Hierarchical Clustering Placement & Routing Output  TV-Pack  U of Toronto  SIS- TEMPLA  陳世梁  Placement & 100 % routing completion  洪偉綸  Performance driven hierarchical clustering  謝禎鋐  Hierarchical clustering for area  林稚忠

10. Algorithm for Technology Mapping Area minimization and Delay (Depth) minimization Select k Mapping Product term check LUT-blocks Single-output PLA blocks

11. Hierarchical Clustering for Area Given pin and capacity constraints of block at each level, minimize the area required (the number of top-level blocks)

12. Min-Cut Based Hierarchical Clustering Step1 :Min-cut (net) based K-way partition by hMetis (initial partition) Step2 :Refine the initial partitions to satisfy pin and area constraints. Step3 :If pin and area constraints can’t be satisfied, then abort, re-start and set K=K+1. Step4 :If it reaches leave block, then outputs the result else do the next level partition

13. Performance Driven Hierarchical Clustering Given timing constraint (required time), pin and block capacity constraints, Minimize the area required (the number of top blocks)

14. Algorithm 1.Clustering Labeling Multiple fan-out node duplication 2.Merging 3-Level hierarchical merge Area constraint Pin constraint

15. Delay & Area Comparisons 174 (1) 198 (1) 1277 (1) 253 (1) 151 (1) 6 52% 6 40% 6 53% 7 40% 8 60% 214 (1.23) 227 (1.15) 1479 (1.16) 286 (1.13) 172 (1.14) 5 63% 5 48% 5 61% 6 47% 7 68% 319 (1.83) 4 75% 1371731213pair 332 (1.67) 4 75% 1072071118 C7552 1743 (1.36) 4 75% 32 1410 C6288 358 (1.41) 5 60% 1231781082 C5315 212 (1.40) 6 83% 8142362alu4 delay#block #PO#PI#PLBCir. P-BasedNo-DupB-DelayP-BasedNo-DupB-Delay

16. Placement and Routing Architecture File Clustered Net-lists P & R Output Placement & Routing on Graph

17. Algorithm for Placement and Routing While( not all nodes placed ) { pick the most critical net-list from the net-list set; for the selected net do compute priority of node for the selected net; select one node based on node ’ s priority; select location for the node based on the current placed nodes; place the node at the selected location; update priority of nets; mark placed nodes; }

18. Future Work Architecture Study Area Speed Expandability Design Tools Technology Mapping Placement and Routing Architecture Design Tools