1. © Digital Integrated Circuits 2nd Sequential Circuits Digital Integrated Circuits A Design Perspective Designing Sequential Logic Circuits Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic November 2002

2. © Digital Integrated Circuits 2nd Sequential Circuits Sequential Logic 2 storage mechanisms positive feedback charge-based

3. © Digital Integrated Circuits 2nd Sequential Circuits Naming Conventions  In our text:  a latch is level sensitive  a register is edge-triggered  There are many different naming conventions  For instance, many books call edge- triggered elements flip-flops  This leads to confusion however

4. © Digital Integrated Circuits 2nd Sequential Circuits Latch versus Register  Latch stores data when clock is low D Clk Q D Q  Register stores data when clock rises Clk D D QQ

5. © Digital Integrated Circuits 2nd Sequential Circuits Latches

6. © Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

7. © Digital Integrated Circuits 2nd Sequential Circuits Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

8. © Digital Integrated Circuits 2nd Sequential Circuits Characterizing Timing Register Latch

9. © Digital Integrated Circuits 2nd Sequential Circuits Maximum Clock Frequency Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay t clk-Q + t p,comb + t setup = T

10. © Digital Integrated Circuits 2nd Sequential Circuits Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

11. © Digital Integrated Circuits 2nd Sequential Circuits Meta-Stability Gain should be larger than 1 in the transition region

12. © Digital Integrated Circuits 2nd Sequential Circuits Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

13. © Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

14. © Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latch

15. © Digital Integrated Circuits 2nd Sequential Circuits Mux-Based Latch NMOS onlyNon-overlapping clocks

16. © Digital Integrated Circuits 2nd Sequential Circuits Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

17. © Digital Integrated Circuits 2nd Sequential Circuits Master-Slave Register Multiplexer-based latch pair

18. © Digital Integrated Circuits 2nd Sequential Circuits Clk-Q Delay

19. © Digital Integrated Circuits 2nd Sequential Circuits Setup Time

20. © Digital Integrated Circuits 2nd Sequential Circuits Reduced Clock Load Master-Slave Register

21. © Digital Integrated Circuits 2nd Sequential Circuits Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

22. © Digital Integrated Circuits 2nd Sequential Circuits Overpowering the Feedback Loop ─ Cross-Coupled Pairs NOR-based set-reset

23. © Digital Integrated Circuits 2nd Sequential Circuits Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic building memory cell

24. © Digital Integrated Circuits 2nd Sequential Circuits Sizing Issues Output voltage dependence on transistor width Transient response

25. © Digital Integrated Circuits 2nd Sequential Circuits Storage Mechanisms D CLK Q Dynamic (charge-based) Static

26. © Digital Integrated Circuits 2nd Sequential Circuits Making a Dynamic Latch Pseudo-Static

27. © Digital Integrated Circuits 2nd Sequential Circuits More Precise Setup Time

28. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

29. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

30. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

31. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

32. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case)

33. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

34. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

35. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

36. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

37. © Digital Integrated Circuits 2nd Sequential Circuits Setup/Hold Time Illustrations Hold-1 case 0

38. © Digital Integrated Circuits 2nd Sequential Circuits Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static

39. © Digital Integrated Circuits 2nd Sequential Circuits Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap

40. © Digital Integrated Circuits 2nd Sequential Circuits Pipelining Reference Pipelined

41. © Digital Integrated Circuits 2nd Sequential Circuits Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1)

42. © Digital Integrated Circuits 2nd Sequential Circuits Including Logic in TSPC AND latch Example: logic inside the latch

43. © Digital Integrated Circuits 2nd Sequential Circuits TSPC Register

44. © Digital Integrated Circuits 2nd Sequential Circuits Pulse-Triggered Latches An Alternative Approach Master-Slave Latches D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered sequential cell:

45. © Digital Integrated Circuits 2nd Sequential Circuits Pulsed Latches

46. © Digital Integrated Circuits 2nd Sequential Circuits Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :

47. © Digital Integrated Circuits 2nd Sequential Circuits Hybrid Latch-FF Timing

48. © Digital Integrated Circuits 2nd Sequential Circuits Latch-Based Pipeline

49. © Digital Integrated Circuits 2nd Sequential Circuits Non-Bistable Sequential Circuits─ Schmitt Trigger VTC with hysteresis Restores signal slopes

50. © Digital Integrated Circuits 2nd Sequential Circuits Noise Suppression using Schmitt Trigger

51. © Digital Integrated Circuits 2nd Sequential Circuits CMOS Schmitt Trigger Moves switching threshold of the first inverter

52. © Digital Integrated Circuits 2nd Sequential Circuits Schmitt Trigger Simulated VTC 2.5 V X (V) V M2 V M1 V in (V) Voltage-transfer characteristics with hysteresis.The effect of varying the ratio of the PMOS deviceM 4. The width isk* 0.5 m. m 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5 V x (V) k = 2 k = 3 k = 4 k = 1 V in (V) 2.0 1.5 1.0 0.5 0.0 0.51.01.52.02.5

53. © Digital Integrated Circuits 2nd Sequential Circuits CMOS Schmitt Trigger (2)

54. © Digital Integrated Circuits 2nd Sequential Circuits Multivibrator Circuits

55. © Digital Integrated Circuits 2nd Sequential Circuits Transition-Triggered Monostable

56. © Digital Integrated Circuits 2nd Sequential Circuits Monostable Trigger (RC-based)

57. © Digital Integrated Circuits 2nd Sequential Circuits Astable Multivibrators (Oscillators) 012N-1 Ring Oscillator simulated response of 5-stage oscillator

58. © Digital Integrated Circuits 2nd Sequential Circuits Relaxation Oscillator

59. © Digital Integrated Circuits 2nd Sequential Circuits Voltage Controller Oscillator (VCO)

60. © Digital Integrated Circuits 2nd Sequential Circuits Differential Delay Element and VCO in 2 two stage VCO v 1 v 2 v 3 v 4 V ctrl V o 2 V o 1 in 1 delay cell simulated waveforms of 2-stage VCO