1. Sprinkler Buddy Presentation #10: “LVS” 4/11/2007 Team M3 Sasidhar Uppuluri Devesh Nema Kalyan Kommineni Kartik Murthy Panchalam Ramanujan Design Manager: Bowei Gai “Low Cost Irrigation Management For Everyone !”

2. Current Status Determine Project Develop Project Specifications Plan Architectural Design Determination of all components in design Detailed logical flowchart Design a Floor Plan Create Structural Verilog Make Transistor Level Schematic Layout Testing (Extraction, LVS, and Analog Sim.) Need to Exhaustively Test

3. Final Design Size Block (# used)Size (um) 40:20 Muxes (4)20 x 80 60:20 Muxes (2)20 x 120 Counter (2)12 x 17 KC ROM (1)181 x 8 P ROM (1)70 x 8 Metric Storage SRAMS (2) 181 x 60 Constant Storage ROM (1) 181 x 8 Floating Point Adder (4) 96x151 Floating Point Multiplier (2) 89 x 40 10 Bit Registers (8)50 x 10 362um x 361 um ~ 1 : 1.0001 aspect ratio.129 mm^2 area.23 Density

4. Overview: FSMs ModeGatesFlopsOutputs Daily Update 97418 Hourly Update 5636 Comp. Mode 3036 Feed Back 3037 Power Gate 6767

5. Layout : FSMs Computation Mode

6. Layout : FSMs Feedback Mode

7. Layout : FSMs Daily Update

8. Layout : Entire Chip

9. Design Challenges and Implementation Decisions For The Past Week Design Challenge Translation to HW Low Power VDD Gating but had to forgo GND Gating

10. For Next Time Simulations.