1. FPGA Technology Mapping

2. 2 Technology mapping:  Implements the optimized nodes of the Boolean network to the target device library.  For FPGA, library elements = LUT −  LUT-based technology mapping Objectives: − Number of LUTs (area) − Signal delay (speed) − Routability − Power (very few work) LUT-Technology Mapping

3. 3 Types of Algorithms Classification: 1.Based on objective functions:  Area-driven  Performance-driven  Routability-driven  Power-driven 2.Based on input network:  Combinational −Assumes fixed positions for sequential elements −Only considers the combinational logic between sequential elements  Sequential −May relocate FFS during mapping (retiming) −Can explore a much larger solution space (better quality) 3.Based on employed transformation technique:  Structural  Functional

4. 4 Types of Algorithms Structural TM:  Does not modify the input netlist (except logic duplication).  Covering a netlist with logic cells (e.g., K-LUTs) of the target FPGAs  Efficient for large designs −Most algorithms are structural. Functional TM:  Boolean transformation/decomposition of the input design into a set of interconnected logic cells  Mixes Boolean optimization with covering  Can potentially explore a larger solution space than structural mapping  Time-consuming −  Restricted to small designs (or small portions of a large design)

5. 5 Fan-in of v or input(v):  the set of nodes whose outputs are inputs of v Fan-out of v or output(v):  the set of nodes, which use the output of v as inputs Primary Input:  a node with no predecessor Primary output:  a node with no successor Level of a node:  the length of the longest path from PI to that node Depth of a graph:  the largest level of a node in the graph K-bounded Boolean network:  if |input(v)|≤ K for all nodes in the graph Definitions

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7. 7 Tree (fan-out-free circuit):   node v, max(fan-out(v)) =1 Forest:  an independent set of trees Leaf-DAG  a combinational circuit in which − no gates have fanout > 1 (except PIs). Definitions

8. 8 Cone C v at node v:  the tree with root v and which spans from v to PIs. K-feasible cone :  C v is K-feasible at node v if: − |input(C v )| ≤ K and − any path connecting a node in C v and v lies entirely in C v Fanout-free cone:  a cone in which the fanouts of every node other than the root are inside the cone −For each node ν, there is a unique maximum fanout-free cone (MFFC v ) A K-feasible Cone at v Definitions −i.e. contains every fanout-free cone rooted at ν

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10. 10 FPGA Tech Mapping Cost (number of inputs) doesn’t always increase with added functions:

11. 11 FPGAs vs. Custom Logic Cost metric for custom static gates is literal:  ax + bx’ has four literals, requires 8 transistors. Cost metric for FPGAs is logic element:  All functions that fit in an LE have the same cost.

12. 12 LUT-technology mapping problem:  Covering a Boolean network with a set of K-feasible cones. − The Boolean network is usually 2-bounded (if not, it is converted to 2-bounded) Graph covering with conesLUT Mapping LUT-Technology Mapping [Chen06]

13. 13 LUT-technology mapping problem:  Covering a Boolean network with a set of K-feasible cones. Graph covering with conesLUT Mapping LUT-Technology Mapping

14. 14 LUT-based logic synthesis Find the largest logic cone that will fit into the LUT: r = q + s’ q = g’ + h s = d’ d = a + b

15. 15 How much fits in a LUT?  One 2-input NAND gate frequently used for comparison.  Approximately 12 ~ 15 gates per four-input LUT.  2 16 functions -> 80 after IO swapping 14 after IO inversion A B C D A B C D

16. 16 LUT-technology mapping problem:  For a combinational logic network,  LUT TM (binding): to find an equivalent logic network, such that −each vertex is associated with a function implementable by a LUT.  Objective: −number of vertices −or minimum critical path delay Starting point:  Decompose into base functions (e.g. ANDs and ORs) LUT-Technology Mapping