1. SYEN 3330 Digital Systems Jung H. Kim Chapter 2-7 1 SYEN 3330 Digital Systems Chapter 2 Part 7

2. SYEN 3330 Digital Systems Chapter 2-7 Page 2 NAND and NOR Implementation

3. SYEN 3330 Digital Systems Chapter 2-7 Page 3 NAND Gates

4. SYEN 3330 Digital Systems Chapter 2-7 Page 4 NAND Gates (Cont.)

5. SYEN 3330 Digital Systems Chapter 2-7 Page 5 NAND Implementation

6. SYEN 3330 Digital Systems Chapter 2-7 Page 6 NAND Implementation (Cont.)

7. SYEN 3330 Digital Systems Chapter 2-7 Page 7 Degenerate AND Term

8. SYEN 3330 Digital Systems Chapter 2-7 Page 8 NAND-NAND Example

9. SYEN 3330 Digital Systems Chapter 2-7 Page 9 NAND-NAND Example

10. SYEN 3330 Digital Systems Chapter 2-7 Page 10 NOR Gates

11. SYEN 3330 Digital Systems Chapter 2-7 Page 11 NOR Implementation

12. SYEN 3330 Digital Systems Chapter 2-7 Page 12 Useful Transformations

13. SYEN 3330 Digital Systems Chapter 2-7 Page 13 Graphical Transformations

14. SYEN 3330 Digital Systems Chapter 2-7 Page 14 General Two-level Implementations

15. SYEN 3330 Digital Systems Chapter 2-7 Page 15 General Implementations (Cont.)

16. SYEN 3330 Digital Systems Chapter 2-7 Page 16 Implementation Example

17. SYEN 3330 Digital Systems Chapter 2-7 Page 17 Implement F in AND-NOR form Implement the network:

18. SYEN 3330 Digital Systems Chapter 2-7 Page 18 Multi-level NAND Implementations Add inverters in two-level implementation into the cost picture Attempt to “combine” inverters to reduce the term count Attempt to reduce literal + term count by factoring expression into POSOP or SOPOS

19. SYEN 3330 Digital Systems Chapter 2-7 Page 19 Multi-level NAND Example 1 F = A B’ + A C’ + B A’ + B C’ = A A’ + A B’ + A C’ + B A’ + B B’ + B C’ = A (A’ + B’ + C’) + B (A’ + B’ + C’) F A C B 7 inputs and 4 gates 15 inputs and 8 gates* * Counting inverters (NOTS) as 1 input and 1 gate

20. SYEN 3330 Digital Systems Chapter 2-7 Page 20 Multilevel NAND Example 2 F = AB + AD’ + BC + CD’ 12 inputs & 5 gates = A(B + D’) + C(B + D’) 8 inputs & 5 gates F A C B D