1. 3. Flip-flops ReturnNext 8.1 Sequential-Circuit Documentation Standards As a whole, basic documentation standards include signal naming, logic symbols, and schematic layout, etc. 8.1.1 General Requirements For sequential circuit, the following ideas are special. 1. State-machine layout 2. Cascaded elements 4. State-machine descriptions 5. Timing diagram 6. Timing specifications

2. 3. Asynchronous preset and inputs may be shown at the top and bottom. 2. A postponed-output indicator is placed on master/slave outputs that change at the end interval during which the clock is asserted. 8.1 Sequential-Circuit Documentation Standards Flip-flops are always drawn as rectangular- shaped symbols – inputs on the left, output on the right, bubbles for active levels, and so on. 8.1.2 Logic Symbols In addition, some specific guidelines apply to flip-flop symbols:. 1. A dynamic indicator is placed on edge- triggered clock inputs. NextBackReturn

3. 3. State diagrams. 2. State tables 8.1 Sequential-Circuit Documentation Standards State-machines can be represented by the following different ways: 8.1.3 State-Machine Descriptions 1. Word descriptions. 4. Transition lists 5. ABEL programs 6. VHDL programs NextBackReturn

4. P664-665 Table 8-1 shows manufacturer’s timing parameters for commonly used flip-flops, registers, and latches in CMOS and TTL. 8.1 Sequential-Circuit Documentation Standards Most timing diagrams show the relationship between the clock and various input, output, and internal signals. 8.1.4 Timing Diagrams and Specifications (See P662-663 Figure 8-1 and Figure 8-2) BackReturn