2. Asynchronous Circuit Verification and Synthesis with Petri Nets J. Cortadella Universitat Politècnica de Catalunya, Barcelona Thanks to: Michael Kishinevsky (Intel Corporation) Alex Kondratyev (The University of Aizu) Luciano Lavagno (Politecnico di Torino) Enric Pastor (Universitat Politècnica de Catalunya) Alex Taubin (The University of Aizu) Alex Yakovlev (University of Newcastle upon Tyne)

3. Motivation u Interfaces are often asynchronous u Subsystems with different clocks often want to talk to each other u Self timing provides functional and temporal modularity u … and no clock skew, low power, low EMI, average performance,...

4. Why Petri nets ? u Formal model to specify causality, concurrency and choice between events u Simple enough to easily derive state-level information (logic synthesis) u Powerful enough to implicitly represent a large state space

5. Outline u Design flow u Synthesis –Specification –State encoding –Logic decomposition u Synthesis of Petri nets u Formal verification

6. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

7. x y z x+ x- y+ y- z+ z- Signal Transition Graph (STG) x y z

8. x y z x+ x- y+ y- z+ z-

9. x+ x- y+ y- z+ z- xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y-

10. xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y- Current state Next state Current state Next state Synchronous Asynchronous

11. xyz 000 x+ 100 y+ z+ y+ 101 110 111 x- 001 011 y+ z- 010 y- Next-state functions

12. x z y

13. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

14. VME bus Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus DSr LDS LDTACK D DTACK Read Cycle

15. STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

16. Choice: Read and Write cycles DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK-DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

17. Choice: Read and Write cycles DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK-DTACK-

18. Circuit synthesis u Goal: –Derive a hazard-free circuit under a given delay model and mode of operation

19. Modes of operation Current state Next state u Fundamental mode –Single-input changes –Multiple-input changes u Input / Output mode –Concurrency circuit / environment

20. STG for the READ cycle LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ LDS LDTACK D DSr DTACK VME Bus Controller

21. Speed independence u Delay model –Unbounded gate / environment delays –Certain wire delays shorter than certain paths in the circuit u Conditions for implementability: –Consistency –Complete State Coding –Output persistency

22. Other synthesis approaches u Burst-mode machines –Mealy-like FSMs –Fundamental mode (slow environment) u VLSI programming –Syntax-directed translation from CSP (“Communicating Sequential Processes”) –No logic synthesis –Circuit size ~ Size of the specification

23. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

24. State Graph (Read cycle) DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

25. Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+

26. Binary encoding of signals DSr+ DTACK- LDS- LDTACK- D- DSr-DTACK+ D+ LDTACK+ LDS+ 10000 10010 10110 0111001110 01100 00110 10110 (DSr, DTACK, LDTACK, LDS, D)

27. QR (LDS+) QR (LDS-) Excitation / Quiescent Regions ER (LDS+) ER (LDS-) LDS- LDS+ LDS-

28. Next-state function 0  1 LDS- LDS+ LDS- 1  0 0  0 1  1 10110

29. Karnaugh map for LDS DTACK DSr D LDTACK 00011110 00 01 11 10 DTACK DSr D LDTACK 00011110 00 01 11 10 LDS = 0 LDS = 1 01-0 000000/1? 1 111 - - - --- ---- - ---- ---

30. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

31. Concurrency reduction LDS- LDS+ LDS- 10110 DSr+

32. Concurrency reduction LDS+LDTACK+D+DTACK+DSr-D- DTACK- LDS-LDTACK- DSr+ (See today’s presentation in this workshop for more details)

33. State encoding conflicts LDS- LDTACK- LDTACK+ LDS+ 10110

34. Signal Insertion LDS- LDTACK- D- DSr- LDTACK+ LDS+ CSC- CSC+ 101101 101100

35. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

36. Complex-gate implementation

37. Specification (STG) State Graph SG with CSC Next-state functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping Designflow

38. Hazards a b c x 0 abcx 1000 1 0 0 1100 b+ 1 1 0 0100 a- 0 1 0 0110 c+ 0 1 1

39. Hazards abcx 1000 1100 b+ 0100 a- 0110 c+ a b z c x 1 0 0 0 0 1000 1 1 0 0 0 1100 1 1 1 0 0 0 1 1 0 0 0100 0 1 1 1 0 0110 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0

40. Decomposition u Global acknowledgement u Generating candidates u Hazard-free signal insertion –Event insertion –Signal insertion

41. Global acknowledgement a b c z a b d y d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

42. a b c z a b d y How about 2-input gates ? d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

43. a b c z a b d y How about 2-input gates ? d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

44. a b c z a b d y How about 2-input gates ? 0 0 d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

45. a b c z a b d y How about 2-input gates ? d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

46. c z d y How about 2-input gates ? a b d-b+d+y+a-y-c+d- c-d+z-b-z+c+a+c-

47. Strategy for correct logic decomposition u Each decomposition defines a new internal signal of the circuit u Method: Insert new internal signals such that –After resynthesis, some large gates are decomposed –The new specification is hazard-free under unbounded gate delays

48. y- z-w- y+x+ z+ x- w+ 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ Decomposition example

49. yz=1 yz=0 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ C C x y x y w z x y z y z w z w z y

50. s- s+ s- s=1 s=0 10011011 1000 1010 0111 0011 y+ x- w+ z+ z- 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 C C x y x y w z x y z w z w z y s y-

51. s- s+ s- s=1 s=0 10011011 1000 1010 0111 0011 y+ x- w+ z+ z- 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 y- z-w- y+x+ z+ x- w+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+

52. C C x y x y w z x y z y z w z w z y yz=1 yz=0 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+

53. s- s+ s=1 s=0 1001 1011 0111 0011 x- w+ z+ 0001 00000101 00100100 0110 x+ w- z- y+ x+ 1001 1000 1010 y+ z- 0111 y- z-w- y+x+ z+ x- w+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ s- s+ z- is delayed by the new transition s- !

54. yz=1 yz=0 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+ C C x y x y w z x y z w z w z yyyyyyy 10011011 1000 1010 0001 00000101 00100100 01100111 0011 y- y+ x- x+ w+ w- z+ z- w- z- y+ x+

55. Signal insertion for function F State Graph F=0F=1 Insertion by input borders F- F+

56. Event insertion a b ER(x) c x x x x b SR(x) a

57. Properties to preserve a a b b a a b b a a b b x a a b b a a b b b a a b b x x a is persistent a is disabled by b = hazards

58. Interactive design flow Petri Net (STG) Transition System Transition System Reachability analysis Transformations + Synthesis

59. Theory of regions (Ehrenfeucht 90, Nielsen 92) a a a b bb c c a b c

60. Synthesis of Petri Nets a a b b b c c c a bc

61. Excitation closure a a b b b c c c bc a

62. b b b b Label splitting a cc d d d d a b b c d

63. Formal verification u Implementability properties –Consistency, persistency, state coding … u Behavioral properties (safeness, liveness) –Mutual exclusion, “ack” after “req”, … u Equivalence checking –Circuit  Specification –Circuit < Specification

64. Property verification: consistency d+ a+ b+ c-a- b-d- c+ Specification a+ a- Property Failure if a+ enabled in specification and a- enabled in property (or viceversa)

65. Correctness: environment  circuit d+ a+ b+ c-a- b-d- c+ a b c d Environment Circuit Failure: circuit produces an event unexpected (not enabled) by the environment

66. Fighting the state explosion u Symbolic methods (BDDs) u Partial order reductions u Petri net unfoldings u Structural theory (invariants)

67. Fighting with state explosion p1 p2 p3 p1 p2 p3 p1 p2 p3 0 1 0 1 0 0 0 0 1 1 1 1

68. Representing Markings p1p1 p2p2 p3p3 p4p4 p5p5 p0p0 p 2 + p 3 + p 5 = 1 p 0 + p 1 + p 4 + p 5 = 1 { p 0, p 3 }  v 0 v 1 v 2 v 3 p 2  v 0 v 1 p 3  v 0 v 1 p 5  v 0 p 0  v 2 v 3 p 1  v 2 v 3 p 4  v 2 Place encoding

69. Summary u Asynchronous design is applicable to –asynchronous interfaces –high-performance computing –low-power design –low-emission design u There is an increased interest of few, but large scale companies: Intel, Philips, Sun, Sharp, ARM, HP, Cogency

70. Summary (continued) u Asynchronous circuits are more difficult to design than synchronous u Formal models and CAD support are essential u Petri nets have been one of the most successful formalisms for modeling asynchronous circuits u Most steps of the design process covered by this tutorial are supported by the tool Petrify