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1UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Is Overlay Error More Important Than Interconnect Variations in Double.

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Presentation on theme: "1UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Is Overlay Error More Important Than Interconnect Variations in Double."— Presentation transcript:

1 1UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Is Overlay Error More Important Than Interconnect Variations in Double Patterning Kwangok Jeong: ECE Dept., UC San Diego Andrew B. Kahng: ECE and CSE Dept., UC San Diego Rasit O. Topaloglu: GLOBALFOUNDRIES, Inc.

2 2UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusions

3 3UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusions

4 4UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Traditional BEOL Variation and Process Sources of variation: Metal/dielectric density- dependent, systematic Random process variation Results of variation Width (W) variation Metal height (H) variation Dielectric thickness (D) variation Traditional backend of the line (BEOL) Process M+1 M-1 M W H D Mask exposure etch Dielectric Resist coating STEPS:MATERIALS: Cu filling Copper

5 5UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusions

6 6UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Double Patterning Lithography Double Patterning Lithography (DPL) Pattern-doubling: ‘2X-resolution’ lithography with traditional ‘1X-resolution’ equipment Options for double patterning lithography Process: Double Exposure (DE) / Double Patterning (DP) / Spacer Double Patterning (SDP) Resist-type: Positive-tone / Negative tone Target Feature: Line / Spacing 1 st Exposure 2 nd Exposure Mask1 Mask2 1X-resolution 1X 2X-resolution 1X Dielectric Mask Resist

7 7UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Double Patterning Lithography Options Double ExposureDouble Patterning Photoresist (a) Positive-tone(b) Negative-tone Target Feature (a) Spaces(b) Lines 1 st Litho-etch 2 nd Litho-etch Spacer-DP Target layer Litho-etch & Spacer Formation Etch Litho Litho-etch mask hardmask positive resist negative resist Cu Dielectric Poly Spacer

8 8UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusions

9 9UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Introduction to the Variability in DPL Overlay error Causes: mask misalignment, material stress-impacted deformations, litho/etch-impacted topography, lens aberration, etc. Results in: Width variation Space (or pitch) variation  Capacitance variation Alignment metric Indirect: Two DPL masks aligned to a reference layer Error: Direct: Second DPL mask aligned to the first DPL mask Error: S S S S Indirect alignment Cc Cg Direct alignment Mask1 Mask2 Reference

10 10UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Overlay Error in Various DPL Options Impact on interconnect parameter in DPL options P (pitch), W (width), W’  W  W”, P’  P  P’’ 1212 1 WW P’P’’ S S 1212 1 W’’W’ PP SS S/2 1212 1 WW’’ PP SS 1212 1 W’ P’’P’ S S Positive DE/DP  SPACE Negative DE/DP  WIDTH Positive SDP  WIDTH & SPACENegative SDP  WIDTH & SPACE

11 11UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Mask Coloring and Layout Examples in DPL Mechanism of misalignment-induced variation (a) DE and DP Process (b) SDP Process 1 2 3 4 5 6 1 2 3 4 5 6 1 4 5 2 3 6 Original patterns Original patterns Coloring Patterns 1 Patterns 2 Coloring Spacer formation (Large spacer) Trim & repair (dark gray) SS Narrow space W 1 2 3 4 5 6 W” Dummy for pattern 6 1 4 5 2 3 6 Spacer (gray) a b

12 12UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusions

13 13UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 TCAD-Based Analysis Setup Test structure Design of experiments (DOE) Full combinations of  W,  H,  D and  S For all DE/DP/SDP with positive/negative-tone resist 3  variation: We assume 20% of nominal value M+1 layer M-1 layer M layer D W H S D: dielectric height W: line width H: line height S: overlay shift 1. for (i = -3 ; i  3 ; i=i+1) { 2. for (j = -3 ; j  3 ; j=j+1) { 3. for (k = -3 ; k  3 ; k=k+1) { 4. for (l = -3 ; l  3 ; l=l+1) { 5. W=W nom + i  W 3  6. H= H nom + j  H 3  7. D= D nom + k  D 3  8. S = S nom + l  S 3  9. run field solver over parameterized structure}}} 8.Find nominal and worst-case capacitance

14 14UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 TCAD-Based Analysis Results Overlay vs.  width vs.  height Indirect alignment shown: Impact of overlay: 0 ~ 2.4% of C-total Impact of  width: -13% ~ 10% of C-total Impact of  height:-32% ~ 18% of C-total Impact of indirect alignment ~ 2x direct alignment Capacitance (aF/um)

15 15UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusion

16 16UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Design-Level Analysis Flow Overlay-aware extraction flow 1. Design GDS TOP.GDS Initial GDS AES core with NanGate 45nm Tech. 2. Split GDS Base GDS Sub-GDS1 Sub-GDS2 3. Pattern Decomposition Sub-GDS1-1 Sub-GDS1-2 Sub-GDS2-1 Sub-GDS2-2 DPL layers Non-DPL layers ILP-based min cost coloring (Kahng et al. ICCAD08) Coloring and Splitting 4. Shift and Merge (Cadence Virtuoso) Shifting and Merging TOP.GDS 5. Resize and Extraction (Synopsys Hercules, Star-RCXT) Resizing

17 17UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Design-Level Analysis DOE Design of Experiments for DE/DP with DA 1.foreach layer  { M2, M3, M4, M5 } 2. decompose layer into layer mask1 and layer mask2 3. foreach S  { -3  /2, -2  /2, -  /2, 0,  /2, 2  /2, 3  /2} 4. shift layer mask1 by S 5. shift layer mask2 by –S 6. end 7. layer  layer mask1 + layer mask2 8. foreach  W  { -3  /2, -2  /2, -  /2, 0,  /2, 2  /2, 3  /2} 9. resize layer by  W 10. end 11. merge with other layers 12. RC-Extraction and Timing Analysis 13. end

18 18UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact on Capacitance Variation Total interconnect capacitance: maximum  C(%) Among top 20% high capacitance nets Impact of overlay < impact of  width Sum of capacitance in the most critical path Critical path has short interconnects  impact of BEOL variation significantly reduces Impact of overlay < impact of  width -3  +3  MinAvgMaxMinAvgMax Overlay-7.7%1.4%9.2%-7.3%1.4%9.7% Width-22.2%4.7%7.1%-3.6%5.3%28.6% Interconnect onlyInterconnect + Gate MinMaxMinMax Overlay-0.08%0.47%-0.04%0.25% Width-1.87%2.59%-0.99%1.38%

19 19UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact on Crosstalk-Induced Delay Maximum coupling induced delay change PrimeTime-SI (Synopsys) is used to find a net that is mostly affected due to crosstalk Temporal/functional filtering is performed Selected net structure A net with relatively small length (~17um) can have >10%  delay changes due to overlay error Cc (pF)Cg (pF)  Delay @Min@Max@Min@MaxMinMax Overlay1.8421.8631.0891.053-0.47%13.1% Width1.8401.9061.0891.120-0.82%15.4% M2 segment: 1.604um M3 segment: 0.78um M4 segment: 14.788um Capacitance when  Delay is minimum Capacitance when  Delay is maximum

20 20UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact on Timing Longest path and total negative slack (TNS) Impact of overlay << impact of  width Longest path delay changes negligibly However, overall timing (TNS) can change significantly Longest path  delay  TNS MinMaxMinMax Overlay-0.06%0.98%3.2%3.8% Width-1.22%2.00%-34.3%49.4% Total Negative Slack (ns) -60 -50 -40 -30 -20 -10 0 -3s-2s-1s0s1s2s3s Interconnect variation Overlay Width

21 21UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Outline Traditional BEOL Variation and Process Double Patterning Lithography (DPL) Overlay Error in Double Patterning TCAD-Based Analysis Design-Level Analysis Conclusions

22 22UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Conclusions We provide a variational interconnect analysis technique for double patterning lithography We analyze interconnect variations due to overlay error in DPL We augment previous work by providing both interconnect and chip-level RC- extraction framework reflecting interconnect variation in a 45nm DPL process We compare the impact of overlay error with traditional interconnect variations Summary of observations Indirect alignment results in higher variation than direct alignment In most analysis, impact of traditional variation source (  width) is larger than that of overlay error, however, overlay error is additive and non-negligible Overlay error can cause up to 10% capacitance variation and 13% increase of crosstalk-induced delay Ongoing/Future Work Impact in the presence of metal fills More in-depth analysis or remaining DPL process options Process sensitivity analysis

23 23UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 BACKUP

24 24UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Misalignment Under M1 Layer (Standard-Cell) Standard cell structure Assumptions There exist a reference coordinate to measure misalignment 10nm misalignment is a maximum displaced distance from the reference coordinate Possible moves Poly1: left 10nm (L) / 0nm (C) /right 10nm (R) Poly2: left 10nm (L) / 0nm (C) /right 10nm (R) M1: left 10nm (L) / 0nm (C) /right 10nm (R) Contact: left 10nm (L) / 0nm (C) /right 10nm (R) All Combinations = 3*3*3*3 = 81 cases Naming convention for each testcase P1{direction}_P2{direction}_C{direction}_M{direction} E.g., “P1C_P2L_CC_MC” means even gates move lef t by 10nm (a)(b) Original MP1P2C BASE

25 25UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Experimental Results on Standard Cell Rise Delay (S) Poly1 (-10nm)Poly1 (0nm)Poly 1(+10nm) Contact (-10nm) Contact (0nm) Contact (+10nm) Contact (-10nm) Contact (0nm) Contact (+10nm) Contact (-10nm) Contact (0nm) Contact (+10nm) Poly2 (-10nm) M1 (-10nm) 1.302E-10 1.307E-10 1.338E-10 M1 (0nm) 1.298E-10 1.303E-10 1.335E-10 M1 (+10nm) 1.299E-10 1.304E-10 1.335E-10 Poly2 (0nm) M1 (-10nm) 1.286E-10 1.291E-101.290E-101.291E-101.296E-101.295E-10 M1 (0nm) 1.286E-10 1.290E-10 1.295E-101.294E-10 M1 (+10nm) 1.282E-10 1.283E-101.286E-10 1.291E-10 Poly2 (+10nm) M1 (-10nm) 1.274E-10 1.278E-10 1.282E-101.281E-10 M1 (0nm) 1.273E-10 1.277E-10 1.281E-101.280E-101.281E-10 M1 (+10nm) 1.273E-10 1.276E-10 1.280E-10 Rise Delay Variation (%) Poly1 (-10nm)Poly1 (0nm)Poly 1(+10nm) Contact (-10nm) Contact (0nm) Contact (+10nm) Contact (-10nm) Contact (0nm) Contact (+10nm) Contact (-10nm) Contact (0nm) Contact (+10nm) Poly2 (-10nm) M1 (-10nm)0.93 1.32 3.72 M1 (0nm)0.62 1.01 3.49 M1 (+10nm)0.70 1.09 3.49 Poly2 (0nm) M1 (-10nm)-0.31 0.080.000.080.470.39 M1 (0nm)-0.31 0.00 0.390.31 M1 (+10nm)-0.62 -0.54-0.31 0.08 Poly2 (+10nm) M1 (-10nm)-1.24 -0.93 -0.62-0.70 M1 (0nm)-1.32 -1.01 -0.70-0.78-0.70 M1 (+10nm)-1.32 -1.09 -0.78 RED: OriginalBlue: Shift one set of gates Green: Shift M1 and Cont. (same direction)

26 26UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 DPL Options Double ExposureDouble PatterningSpacer-DP Photoresist Printed Feature mask positive resist negative resist After exposure & etch Dielectric After Cu filling (a) Positive-tone(b) Negative-tone Cu interconnect mask positive resist After exposure & etch Dielectric (a) Spaces (Trench-First)(b) Lines Cu interconnect Poly Target layer Resist Hardmask Buffer oxide Hardmask Target layer 1 st Litho-etch Spacer formationOxide depo. CMP Spacer removal 2 nd etch Mask Target layer Resist Hardmask 1 st Litho-etch 2 nd Litho-etch Mask1 Mask2 Target layer Resist 1 st Exposure 2 nd Exposure Mask1 Mask2

27 27UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact of Overlay in Positive DE/DP 1212 1 WW P’P’’ S S mask1 mask2 (misaligned to left) Positive photoresist Dielectric After exposure + etch After filling Cu Cu

28 28UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact of Overlay in Negative DE/DP 1212 1 W’’W’ PP SS S/2 mask1 mask2 (misaligned to left) Negative photoresist Dielectric After exposure + etch After filling Cu Cu

29 29UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact of Overlay in Positive SDP 1212 1 WW’’ PP SS Primary patterns Dielectric After exposure + etch After filling Cu Spacers (act as if masks) (kind of) Positive photoresist Cu

30 30UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Impact of Overlay in Positive SDP 1212 1 W’ P’’P’ SS Primary patterns Dielectric After exposure + etch After filling Cu Spacers (act as if masks) (kind of ) Negative photoresist Cu

31 31UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Overlay error can cause more than +/- 10% capacitance variation within a die  This variation must be back-annotated to timing analysis to reduce unnecessary guardbanding Capacitance Variation (%) Electrical Impacts: Capacitance Variation

32 32UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 P-DE/DPN-DE/DPP-SDPN-SDP M2 M4 |S|/2|S||S|/2 |S||S|/2

33 33UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 A net has maximum crosstalk-induced delay SDP shows more sensitivity  tighten overlay spec P-DE/DP shows least sensitivity  lessen overlay spec Maximum Crosstalk Induced Delay P-DE/DPN-DE/DPP-SDPN-SDP M4 |S||S|/2 M2 M4M2 M4 w/o metal fillw/ metal fill A B

34 34UCSD VLSI CAD Laboratory / GLOBALFOUNDRIES, Inc. - SLIP Workshop, July 26 2009 Total Negative Slack Variation SDP, especially for lower layer (smaller feature), shows more sensitivity  tighter overlay spec

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