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CSCE 212 Introduction to Computer Architecture
Instructor: Jason D. Bakos
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Abstraction Abstration used to manage complexity of design
Hide details that are not important Application Software Programs Compiler Operating Systems Device Drivers Architecture Instructions Registers Micro-architecture Datapaths Controllers Logic Adders Memories Digital circuits AND gates NOT gates Analog circuits Amplifiers Filters Devices Transistors Diodes Physics Electrons 145/146/240/245 311 212 211 211/611 ELCT 371 330
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Domains and Levels of Modeling
Structural Functional high level of abstraction low level of abstraction “Y-chart” from Gajski & Kahn Geometric
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Domains and Levels of Modeling
Structural Functional Algorithm (behavioral) Register-Transfer Language Boolean Equation Differential Equation “Y-chart” from Gajski & Kahn Geometric
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Domains and Levels of Modeling
Structural Functional Processor-Memory Switch Register-Transfer Gate Transistor “Y-chart” from Gajski & Kahn Geometric
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Domains and Levels of Modeling
Structural Functional Polygons Sticks Standard Cells Floor Plan “Y-chart” from Gajski & Kahn Geometric
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Structure
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MIPS Microarchitecture
RTL (datapath) fetch instruction 1. Address <= PC 2. MemRead 3. PC <= PC + 1 4. IR <= MemData Control fetch instruction 1. IorD = 0 2. MemRead = 1 3. PCEn = 1 ALUSrcA = 0 ALUSrcB = 01 ALUOp = ADD PCSource = 01 4. IRWrite = 1
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Structure
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Logic Synthesis Behavior: S = A + B
Assume A is 2 bits, B is 2 bits, C is 3 bits A B C 00 (0) 000 (0) 01 (1) 001 (1) 10 (2) 010 (2) 11 (3) 011 (3) 100 (4) 101 (5) 110 (6)
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Logic Gates inv NAND2 NAND3 NOR2
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Positive edge-sensitive latch
Latches Positive edge-sensitive latch
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Elements
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Semiconductors Silicon is a group IV element (4 valence electrons, shells: 2, 8, 18, 32…) Forms covalent bonds with four neighbor atoms (3D cubic crystal lattice) Si is a poor conductor, but conduction characteristics may be altered Add impurities/dopants (replaces silicon atom in lattice): Makes a better conductor Group V element (phosphorus/arsenic) => 5 valence electrons Leaves an electron free => n-type semiconductor (electrons, negative carriers) Group III element (boron) => 3 valence electrons Borrows an electron from neighbor => p-type semiconductor (holes, positive carriers) + - - + + + + + + + - - - - - - P-N junction forward bias reverse bias
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MOSFETs Metal-poly-Oxide-Semiconductor structures built onto substrate
negative voltage (rel. to body) (GND) positive voltage (Vdd) NMOS/NFET PMOS/PFET + + + - - - - - - + + + current current channel shorter length, faster transistor (dist. for electrons) body/bulk GROUND body/bulk HIGH (S/D to body is reverse-biased) Metal-poly-Oxide-Semiconductor structures built onto substrate Diffusion: Inject dopants into substrate Oxidation: Form layer of SiO2 (glass) Deposition and etching: Add aluminum/copper wires
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IC Fabrication Chips are fabricated using set of masks Basic steps
Photolithography Basic steps oxidize apply photoresist remove photoresist with mask HF acid eats oxide but not photoresist pirana acid eats photoresist ion implantation (diffusion, wells) vapor deposition (poly) plasma etching (metal)
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Layout 3-input NAND
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Cell Library (Snap Together)
Layout
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Layout
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Synthesized and P&R’ed MIPS Architecture
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IC Fabrication
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8” Wafer 8 inch (200 mm) wafer containing Pentium 4 processors
165 dies, die area = 250 mm2, 55 million transistors, .18mm
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Another 8” Wafer
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Feature Size Shrink minimum feature size…
Smaller L decreases carrier time and increases current Therefore, W may also be reduced for fixed current Cg, Cs, and Cd are reduced Transistor switches faster (~linear relationship)
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Minimum Feature Size Upcoming milestones:
Year Processor Speed Process 1982 i286 MHz 1.5 mm 1986 i386 16 – 40 MHz mm 1989 i486 MHz .8 mm 1993 Pentium MHz mm 1995 Pentium Pro MHz mm 1997 Pentium II MHz mm 1999 Pentium III 450 – 1400 MHz mm 2000 Pentium 4 1.3 – 3.8 GHz mm 2005 Pentium D 2.66 – 3.6 GHz mm 2006 Core 2 1.06 – 3 GHz .065 mm 2007 Xeon 5400 3 – 3.2 GHz .045 mm Upcoming milestones: 32 nm ( ), 22 nm ( ), 16 nm (2013)
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Clock Speed Clock speed is affected by: Execution time =
Fabrication technology Architecture: how much work performed in a single cycle Execution time = instructions per program * cycles per instruction * seconds per cycle Now we must add to the product: (number of program threads / number of processor cores)
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Core 2 Duo (2007) has ~300M transistors
Integration Density Core 2 Duo (2007) has ~300M transistors
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Integration Density
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Microprocessor Technology
Advances in fabrication (lithography, photoresist, metal layers) …faster transistor switching (faster processor) …smaller transistors/wires …higher integration density …more “real estate” …architectural improvements!
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Microarchitectural Parallelism
Parallelism => perform multiple operations simultaneously Instruction-level parallelism Execute multiple instructions at the same time Multiple issue Out-of-order execution Speculation Branch prediction Thread-level parallelism (hyper-threading) Execute multiple threads at the same time on one CPU Threads share memory space and pool of functional units Chip multiprocessing Execute multiple processes/threads at the same time on multiple CPUs Cores are symmetrical and completely independent but share a common level-2 cache
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