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Saman Amarasinghe 16.035 ©MIT Fall 1998 Simple Machine Model Instructions are executed in sequence –Fetch, decode, execute, store results –One instruction.

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Presentation on theme: "Saman Amarasinghe 16.035 ©MIT Fall 1998 Simple Machine Model Instructions are executed in sequence –Fetch, decode, execute, store results –One instruction."— Presentation transcript:

1 Saman Amarasinghe 16.035 ©MIT Fall 1998 Simple Machine Model Instructions are executed in sequence –Fetch, decode, execute, store results –One instruction at a time For branch instructions, start fetching from a different location if needed –Check branch condition –Next instruction may come from a new location given by the branch instruction

2 Saman Amarasinghe 26.035 ©MIT Fall 1998 Simple Execution Model 5 Stage pipe-line Fetch: get the next instruction Decode: figure-out what that instruction is Execute: Perform ALU operation –address calculation in a memory op Memory: Do the memory access in a mem. Op. Write Back: write the results back fetchdecodeexecutememorywriteback

3 Saman Amarasinghe 36.035 ©MIT Fall 1998 Simple Execution Model IF DEEXEMEMWB IF DEEXEMEMWB Inst 1 Inst 2 time

4 Saman Amarasinghe 46.035 ©MIT Fall 1998 Simple Execution Model IF DEEXEMEMWB IF DEEXEMEMWB Inst 1 Inst 2 time IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB IF DEEXEMEMWB Inst 1 Inst 2 Inst 3 Inst 4 Inst 5

5 Saman Amarasinghe 56.035 ©MIT Fall 1998 From a Simple Machine Model to a Real Machine Model Many pipeline stages –MIPS R4000 has 8 stages Different instructions taking different amount of time to execute –mult 10 cycles –div69 cycles –ddiv133 cycles Hardware to stall the pipeline if an instruction uses a result that is not ready

6 Saman Amarasinghe 66.035 ©MIT Fall 1998 Real Machine Model cont. Most modern processors have multiple execution units (superscalar) –If the instruction sequence is correct, multiple operations will happen in the same cycles –Even more important to have the right instruction sequence

7 Saman Amarasinghe 76.035 ©MIT Fall 1998 Instruction Scheduling Reorder instructions so that pipeline stalls are minimized

8 Saman Amarasinghe 86.035 ©MIT Fall 1998 Constraints On Scheduling Data dependencies Control dependencies Resource Constraints

9 Saman Amarasinghe 96.035 ©MIT Fall 1998 Data Dependency between Instructions If two instructions access the same variable, they can be dependent Kind of dependencies –True: write  read –Anti: read  write –Output: write  write What to do if two instructions are dependent. –The order of execution cannot be reversed –Reduce the possibilities for scheduling

10 Saman Amarasinghe 106.035 ©MIT Fall 1998 Computing Dependencies For basic blocks, compute dependencies by walking through the instructions Identifying register dependencies is simple –is it the same register? For memory accesses –simple: base + offset1 != base + offset2 –data dependence analysis: a[2i] != a[2i+1] –interprocedural analysis: global != parameter –pointer alias analysis: p1 != p

11 Saman Amarasinghe 116.035 ©MIT Fall 1998 Representing Dependencies Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies

12 Saman Amarasinghe 126.035 ©MIT Fall 1998 Representing Dependencies Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies 1: r2 = *(r1 + 4) 2: r3 = *(r1 + 8) 3: r4 = r2 + r3 4: r5 = r2 - 1

13 Saman Amarasinghe 136.035 ©MIT Fall 1998 Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies 1: r2 = *(r1 + 4) 2: r3 = *(r1 + 8) 3: r4 = r2 + r3 4: r5 = r2 - 1 3 1 Representing Dependencies 2 4

14 Saman Amarasinghe 146.035 ©MIT Fall 1998 Using a dependence DAG, one per basic block Nodes are instructions, edges represent dependencies 1: r2 = *(r1 + 4) 2: r3 = *(r1 + 8) 3: r4 = r2 + r3 4: r5 = r2 - 1 Edge is labeled with Latency: –v(i  j) = delay required between initiation times of i and j minus the execution time required by i 3 1 Representing Dependencies 2 4 22 2

15 Saman Amarasinghe 156.035 ©MIT Fall 1998 Example 1: r2 = *(r1 + 4) 2: r3 = *(r2 + 4) 3: r4 = r2 + r3 4: r5 = r2 - 1 3 12 4 22 2 3

16 Saman Amarasinghe 166.035 ©MIT Fall 1998 Another Example 1: r2 = *(r1 + 4) 2: *(r1 + 4) = r3 3: r3 = r2 + r3 4: r5 = r2 - 1 3 12 4

17 Saman Amarasinghe 176.035 ©MIT Fall 1998 Another Example 1: r2 = *(r1 + 4) 2: *(r1 + 4) = r3 3: r3 = r2 + r3 4: r5 = r2 - 1 3 12 4 22 1 1

18 Saman Amarasinghe 186.035 ©MIT Fall 1998 Control Dependencies and Resource Constraints For now, lets only worry about basic blocks For now, lets look at simple pipelines

19 Saman Amarasinghe 196.035 ©MIT Fall 1998 Example 1: LAr1,array 2: LDr2,4(r1) 3: ANDr3,r3,0x00FF 4: MULCr6,r6,100 5: STr7,4(r6) 6: DIVCr5,r5,100 7: ADDr4,r2,r5 8: MULr5,r2,r4 9: STr4,0(r1)

20 Saman Amarasinghe 206.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1)

21 Saman Amarasinghe 216.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1

22 Saman Amarasinghe 226.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1

23 Saman Amarasinghe 236.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 12

24 Saman Amarasinghe 246.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 123

25 Saman Amarasinghe 256.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234

26 Saman Amarasinghe 266.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234

27 Saman Amarasinghe 276.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 5

28 Saman Amarasinghe 286.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56

29 Saman Amarasinghe 296.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56

30 Saman Amarasinghe 306.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 7

31 Saman Amarasinghe 316.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 7

32 Saman Amarasinghe 326.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 78

33 Saman Amarasinghe 336.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 789

34 Saman Amarasinghe 346.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 789 14 cycles!

35 Saman Amarasinghe 356.035 ©MIT Fall 1998 List Scheduling Algorithm Idea –Do a topological sort of the dependence DAG –Consider when an instruction can be scheduled without causing a stall –Schedule the instruction if it causes no stall and all its predecessors are already scheduled Optimal list scheduling is NP-complete –Use heuristics when necessary

36 Saman Amarasinghe 366.035 ©MIT Fall 1998 List Scheduling Algorithm Create a dependence DAG of a basic block Topological Sort READY = nodes with no predecessors Loop until READY is empty Schedule each node in READY when no stalling Update READY

37 Saman Amarasinghe 376.035 ©MIT Fall 1998 Heuristics for selection Heuristics for selecting from the READY list –pick the node with the longest path to a leaf in the dependence graph –pick a node with most immediate successors –pick a node that can go to a less busy pipeline (in a superscalar)

38 Saman Amarasinghe 386.035 ©MIT Fall 1998 Heuristics for selection pick the node with the longest path to a leaf in the dependence graph Algorithm (for node x) –If no successors d x = 0 –d x = MAX( d y + c xy ) for all successors y of x –reverse breadth-first visitation order

39 Saman Amarasinghe 396.035 ©MIT Fall 1998 Heuristics for selection pick a node with most immediate successors Algorithm (for node x): –f x = number of successors of x

40 Saman Amarasinghe 406.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1)

41 Saman Amarasinghe 416.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 1: LAr1,array 2: LDr2,4(r1) 3: ANDr3,r3,0x00FF 4: MULCr6,r6,100 5: STr7,4(r6) 6: DIVCr5,r5,100 7: ADDr4,r2,r5 8: MULr5,r2,r4 9: STr4,0(r1)

42 Saman Amarasinghe 426.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3

43 Saman Amarasinghe 436.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0

44 Saman Amarasinghe 446.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3

45 Saman Amarasinghe 456.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3

46 Saman Amarasinghe 466.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7

47 Saman Amarasinghe 476.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4

48 Saman Amarasinghe 486.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5

49 Saman Amarasinghe 496.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0

50 Saman Amarasinghe 506.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { }

51 Saman Amarasinghe 516.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { } 1, 3, 4, 6

52 Saman Amarasinghe 526.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 6, 1, 4, 3 } 1, 3, 4, 6

53 Saman Amarasinghe 536.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 6, 1, 4, 3 }

54 Saman Amarasinghe 546.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 6, 1, 4, 3 } 6

55 Saman Amarasinghe 556.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 1, 4, 3 } 6

56 Saman Amarasinghe 566.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 1, 4, 3 } 6

57 Saman Amarasinghe 576.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 1, 4, 3 } 61

58 Saman Amarasinghe 586.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 4, 3 } 61 2

59 Saman Amarasinghe 596.035 ©MIT Fall 1998 Example 1 6 8279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 61

60 Saman Amarasinghe 606.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 61

61 Saman Amarasinghe 616.035 ©MIT Fall 1998 Example 1 6 8 2 79 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 61

62 Saman Amarasinghe 626.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 2, 4, 3 } 612

63 Saman Amarasinghe 636.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 4, 3 } 612 7

64 Saman Amarasinghe 646.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

65 Saman Amarasinghe 656.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

66 Saman Amarasinghe 666.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

67 Saman Amarasinghe 676.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 612

68 Saman Amarasinghe 686.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 4, 3 } 6124

69 Saman Amarasinghe 696.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3 } 6124 5

70 Saman Amarasinghe 706.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 6124

71 Saman Amarasinghe 716.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 6124

72 Saman Amarasinghe 726.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 6124

73 Saman Amarasinghe 736.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 7, 3, 5 } 61247

74 Saman Amarasinghe 746.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5 } 61247 8, 9

75 Saman Amarasinghe 756.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5, 8, 9 } 61247

76 Saman Amarasinghe 766.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5, 8, 9 } 61247

77 Saman Amarasinghe 776.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 3, 5, 8, 9 } 612473

78 Saman Amarasinghe 786.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 612473

79 Saman Amarasinghe 796.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 612473

80 Saman Amarasinghe 806.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 612473

81 Saman Amarasinghe 816.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 5, 8, 9 } 6124735

82 Saman Amarasinghe 826.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 6124735

83 Saman Amarasinghe 836.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 6124735

84 Saman Amarasinghe 846.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 6124735

85 Saman Amarasinghe 856.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 8, 9 } 61247358

86 Saman Amarasinghe 866.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 61247358

87 Saman Amarasinghe 876.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 61247358

88 Saman Amarasinghe 886.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 61247358

89 Saman Amarasinghe 896.035 ©MIT Fall 1998 Example 1 6 8 2 7 9 1 1 3 4 1 4 5 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { 9 } 612473589

90 Saman Amarasinghe 906.035 ©MIT Fall 1998 Example 168279 1 1 3 4 1 45 3 3 d=0 d=3 d=7d=4 d=5 f=1f=0 f=1 f=2 f=0 READY = { } 612473589

91 Saman Amarasinghe 916.035 ©MIT Fall 1998 Example 612473589 Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 9 cycles

92 Saman Amarasinghe 926.035 ©MIT Fall 1998 Example Results In 1: LAr1,array1 cycle 2: LDr2,4(r1)1 cycle 3: ANDr3,r3,0x00FF1 cycle 4: MULCr6,r6,1003 cycles 5: STr7,4(r6) 6: DIVCr5,r5,1004 cycles 7: ADDr4,r2,r51 cycle 8: MULr5,r2,r43 cycles 9: STr4,0(r1) 1234st 56 789 14 cycles Vs 9 cycles 612473589

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