1. Multiplexers Lecture L6.6v Section 6.2

2. Multiplexers A Digital Switch A 2-to-1 MUX A 4-to-1 MUX A Quad 2-to-1 MUX The Verilog if…else Statement TTL Multiplexer

3. Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3

4. Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 0 A multiplexer is a digital switch

5. Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 0 1

6. Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 1 0

7. Multiplexers Y 4 x 1 MUX s0s1 C0 C1 C2 C3 Y s1s0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 1

8. A 2 x 1 MUX Z = A & ~s0 | B & s0

9. A 4 x 1 MUX A = ~s0 & C0 | s0 & C1 B = ~s0 & C2 | s0 & C3 Z = ~s1 & A | s1 & B Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3)

10. A 4 x 1 MUX Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3) Z = ~s1 & ~s0 & C0 | ~s1 & s0 & C1 | s1 & ~s0 & C2 | s1 & s0 & C3

11. Y s 0 A 1 B Problem How would you make a Quad 2-to-1 MUX? s [A3..A0] [B3..B0] [Y3..Y0] Quad 2-to-1 MUX

12. mux.v module mux24(A,B,s,Y); input [3:0] A; input [3:0] B; input s; output [3:0] Y; wire [3:0] Y; assign Y = {4{~s}} & A | {4{s}} & B; endmodule s [A3..A0] [B3..B0] [Y3..Y0] Quad 2-to-1 MUX

13. mux.v module mux24(A,B,s,Y); input [3:0] A; input [3:0] B; input s; output [3:0] Y; wire [3:0] Y; always @(A,B,s) if(s == 0) Y = A; else Y = B; endmodule s [A3..A0] [B3..B0] [Y3..Y0] Quad 2-to-1 MUX

14. TTL Multiplexer 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 GND Vcc1G B 1C3 1C2 1C1 1C0 1Y 2G A 2C3 2C2 2C1 2C0 2Y 74LS153 X X X X X X 1 0 0 0 0 X X X 0 0 0 0 1 X X X 0 1 0 1 X 0 X X 0 0 0 1 X 1 X X 0 1 1 0 X X 0 X 0 0 1 0 X X 1 X 0 1 1 1 X X X 0 0 0 1 1 X X X 1 0 1 B A C0 C1 C2 C3 G Y Dual 4-to-1-line multiplexer