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Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design.

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Presentation on theme: "Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design."— Presentation transcript:

1 Idongesit Ebong (1-1) Jenna Fu (1-2) Bowei Gai (1-3) Syed Hussain (1-4) Jonathan Lee (1-5) Design Manager: Myron Kwai Overall Project Objective: Design a chip as part of a system that accommodates the growing demand for radio frequency identification (RFID) technology while creating a quicker, more convenient shopping experience. Presentation #12: Smart Cart 525 Stage XII: 11 April 2005 Final LVS and Simulation

2 Status Design Proposal Project chosen Verilog obtained/modified Architecture Proposal Behavioral Verilog simulated Size estimates/floorplanning Gate-level implementation simulated in Verilog Floorplan and more accurate transistor count Schematic Design Component Layout Functional Block Layout DRC of functional blocks LVS of functional blocks Chip Level Layout Full chip LVS  Simulations (99%) Schematic with loaded inputs/outputs ExtractedRC  Full chip simulation (both parts verified separately)

3 Design Decisions Changed buffers in multiplier to sized-buffers Minor modifications to layout to save a little more space Testing  Used mostly random test vectors, but chose specific values for tax to affect multiplier and increase propagation time (to test critical path)

4 Final Chip Layout

5 Design Specifications Area:92,879.5 μm 2 # of Transistors:22,120 Density: (transistors/μm 2 ).238 Aspect ratio:1.13

6 Final Simulations (Full Chip Output—Verilog) 0 lastPrice= x, finalTotal= x, Encrypted_Datareg=xxxxxxxx, Done=x UPDATING COUPONS AND PRICES 15 lastPrice= x, finalTotal= 0, Encrypted_Datareg=xxxxxxxx, Done=x ADDING ITEMS ================================================= Adding 1000 with price of 500c 245 lastPrice= 500, finalTotal= 0, Encrypted_Datareg=xxxxxxxx, Done=x 255 lastPrice= 500, finalTotal= 500, Encrypted_Datareg=xxxxxxxx, Done=x Adding 1010 with price of 750c 275 lastPrice= 750, finalTotal= 1250, Encrypted_Datareg=xxxxxxxx, Done=x Adding 0000 with price of 900c 295 lastPrice= 900, finalTotal= 2150, Encrypted_Datareg=xxxxxxxx, Done=x REMOVING ITEMS ================================================= Removing 1010 with price of 750c 315 lastPrice= 750, finalTotal= 1400, Encrypted_Datareg=xxxxxxxx, Done=x APPLYING COUPON ================================================= Applying 0000 Coupon of value 20c 335 lastPrice= 20, finalTotal= 1380, Encrypted_Datareg=xxxxxxxx, Done=x PERFORMING CHECKOUT ================================================= Applying Tax of 3 percent 365 lastPrice= 20, finalTotal= 142140, Encrypted_Datareg=xxxxxxxx, Done=x Take 2 decimal places to the left to get answer in cents Take 4 decimal places to the left to get answer in dollars COLLECTING CREDIT CARD INFO ================================================= 420Done 445 lastPrice= 20, finalTotal= 142140, Encrypted_Datareg=xxxxxxxx, Done=0 555 lastPrice= 20, finalTotal= 142140, Encrypted_Datareg=991b8daf, Done=1

7 Final Simulations (Total Output—Schematic)

8 Final Simulations (Total Output--ExtractedRC)

9 Final Simulations (Last Price Output--Schematic)

10 Final Simulations (Last Price Output--ExtractedRC)

11 Final Simulations (Encryption Final Output--Schematic)

12 Final Simulations (Encryption Final Output--ExtractedRC)

13 Final Simulations (Critical Path--Multiplier) Propagation time: 5.88 ns

14 Problems & Questions Encryption outputs incorrect in full chip simulation  Second clock speed needs to be at least four times faster to fix this We can’t run a complete full chip simulation at this point in time  Not enough hard drive space


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