1. Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies Kunal K. Dave ATI Research INC. Vishwani D. Agrawal Dept. of ECE, Auburn University Michael L. Bushnell Dept. of ECE, Rutgers University

2. 7/14/2015Kunal Dave - VLSI Design '052 About this work !!! This work is motivated by a fault independent redundancy identification method using implication graphs. We use contrapositive rule to derive new partial implication nodes, oring nodes, to enhance the logic information in the implication graph. Develop new algorithms that dynamically update the transitive closure graph while extracting implications from a logic network – described in the paper and Master’s thesis. Apply new implication graph and dynamic update algorithms to redundancy identification to obtain better performance.

3. 7/14/2015Kunal Dave - VLSI Design '053 Implication Graph An implication graph (IG)  Digital circuit in the form of a set of binary and higher-order relations. a b c Boolean equation AND: c = ab Boolean false function * AND: ab c = 0 ac + bc + abc = 0 Chakradhar et al. -- IEEE-D&T, 1990 Henftling and Wittmann – AEU, 1995 Implication graph with with anding nodes a b c c b a Λ3Λ3 Λ1Λ1 Λ2Λ2

4. 7/14/2015Kunal Dave - VLSI Design '054 Observability Implications b OaOa OcOc Λ3Λ3 b b Λ1Λ1 Λ2Λ2 OcOc OaOa OcOc OaOa b a s OsOs OsOs O sa O sb Observability nodes – Agrawal, Lin and Bushnell -- ATS, 1996 a b c

5. 7/14/2015Kunal Dave - VLSI Design '055 Transitive Closure Transitive closure (TC) of a directed graph contains the same set of nodes as the original graph. If there is a directed path from node a to b, then the transitive closure contains an edge from a to b. A graph Transitive closure b c d a b c d a A Graph Transitive Closure

6. 7/14/2015Kunal Dave - VLSI Design '056 Oring Nodes Expansion of Boolean false function AND : ac + bc + abc = 0 a c c a Contrapositive b c c b Contrapositive (a Λ b) cc (a Λ b) Contrapositive c (a V b) De-Morgan Λ3Λ3 a b c c b a Λ1Λ1 Λ2Λ2 a b c c b a Λ1Λ1 V1V1 Enhanced Implication graph (previous) New Implication graph (present)

7. 7/14/2015Kunal Dave - VLSI Design '057 Redundancy Identification Obtain an implication graph from the circuit topology and compute transitive closure. There are 8 different conditions on the basis of which a fault is said to be redundant.* Examples:  If node c implies c then s-a-0 fault on line c is redundant.  If node O c implies O c then c is unobservable and both s-a-0 and s-a-1 faults on line c are redundant. No Search is performed to find redundant faults. A Subset of total redundant faults is found. * Agrawal et al. -- ATS, 1996 & Gaur et al. -- DELTA, 2002

8. 7/14/2015Kunal Dave - VLSI Design '058 An Example V1V1 a b c c b a Λ1Λ1 Λ2Λ2 d d V2V2 a b c d e e e Λ4Λ4 Λ3Λ3 s-a-0 s-a-1 s-a-0 s-a-1 Portion of the implication graph containing controllability nodes (Observability nodes are not shown)

9. 7/14/2015Kunal Dave - VLSI Design '059 Results on ISCAS Circuits Circuit Total faults Redundant faults identified and run time TRAN Chakradhar et al. FIRE Iyer and Abramovici TC M Mehta et al. Our Algorithm Red. faults CPU Sec. a Red. Faults CPU Sec. b Red. Faults CPU Sec. a Red. Faults CPU Sec. a c19081879713.061.823.255.7 c2670274711595.2291.5594.0696.0 c75527550131308.0304.75111.56517.7 s1238c13556917.461.9202.6515.4 a Sun SPARC5 CPU Sec. b Sun SPARC2 CPU Sec.

10. 7/14/2015Kunal Dave - VLSI Design '0510 ISCAS ’85 -- C1908 979 887 74 952 953 949 926 Redundant faults (s-a-1) 0 0 0/1

11. 7/14/2015Kunal Dave - VLSI Design '0511 ISCAS ’85 -- C5315 1 0/1 1 1 1 1 1 PI PO 0 0 0 0 0/1 0 1 1 1 Redundant fault (s-a-1)

12. 7/14/2015Kunal Dave - VLSI Design '0512 ISCAS ’85 -- C5315 1 0/1 1 0 0 0 1 PI PO 1 1 1 0/1 0 1 0 Redundant fault (s-a-1) 1 1

13. 7/14/2015Kunal Dave - VLSI Design '0513 Conclusion – Future Work Contributions  New partial implication structure called oring node enhances implication graph of logic circuits; more complete and more compact than the graph with just anding nodes.  New algorithms dynamically update the transitive closure every time a new implication edge is added; greater efficiency over complete re-computation.  New and improved fault-independent redundancy identification. New techniques can be further explored:  Fanout stem unobservability – proposed solution.  Equivalence checking.  Test generation.  Redundancy removal – only one fault is removed at a time.

14. 7/14/2015Kunal Dave - VLSI Design '0514 Thank You