1. Implementation of DSP Algorithm on SoC

2. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak The project is conducted with cooperation of Rafael. winter 2003/2004

3. Project Goals - Review Studying and investigating the architecture of System on Programmable Chip (SoC). Studying and investigating the architecture of System on Programmable Chip (SoC). Deciding on the Software/Hardware partition to be implemented. Deciding on the Software/Hardware partition to be implemented. Implementing a signal processing algorithm on the chosen platform. Implementing a signal processing algorithm on the chosen platform. First Semester: Full understanding of the elements and studied environments. Full understanding of the elements and studied environments. Running examples on the evaluation board. Running examples on the evaluation board.

4. Project Schedule First Semester 1. Studying the VHDL programming language. 2. Get familiar with the FPGA structure. 3. Get familiar with the FPGA design process. 4. Studying Simulation and Synthesis programs. 5. Studying the Xilinx ’ s FPGA. 6. Studying Xilinx ’ s P&R program.

5. 1. Studying the VHDL Programming Language. Self-study from the Digital Lab ’ s CD and Guidance brochure of SITAL Technology. Self-study from the Digital Lab ’ s CD and Guidance brochure of SITAL Technology. ‘ Rules of VHDL writing for synthesis ’ – two tutorials given by the digital lab. ‘ Rules of VHDL writing for synthesis ’ – two tutorials given by the digital lab. Writing a FIFO example, Using a RAMB4_S1_S1 (4K*1 bit) component, of several implementations: Writing a FIFO example, Using a RAMB4_S1_S1 (4K*1 bit) component, of several implementations: 1. Building a 4K*8 bit memory space. 2. Buliding a 8K*1 bit memory space. 3. FIFO with Overflow. 4. Synchronized Fifo – using Empty/Full Flags.

6. 2. Get Familiar with the FPGA Structure. Field Programmable Gate Array LUT FFLUT Logic Cell Slice CLB=8 LC = 4 Slices FPGA CLB RAM

7. 3. Get Familiar with the FPGA Design Process. FPGA Design: 1. Requirements – the purpose and functionality of the device. 2. Architecture – Interfaces (In/Out signals) and a general block scheme. 3. Design – a specification of each block in the block scheme. 4. Implementation – writing the VHDL Code. 5. Simulations – both logical and using test vectors, to ensure rightness of previous stages. 6. Synthesis – building Gate-Level implementation. 7. Place & Route – building and downloading a bitstream for the final device. 8. Integration and debugging.

8. 3. Get Familiar with the FPGA Design Process (cont.) Flow: Editor Simulator Synth. P&R FPGA.VHD.EDIF.EDN.BIT.EXO

9. 4. Studying Simulation and Synthesis Programs. 4.1 Simulation program - ModelSim

10. 4. Studying Simulation and Synthesis Programs (cont.) 4.2 Synthesis program Input:.VHD file with the code. Input:.VHD file with the code. Output:.EDIF file with the implementation of the design using the logic units of the chosen FPGA. Output:.EDIF file with the implementation of the design using the logic units of the chosen FPGA. Optimization of the design by adding constrains on signals and critical paths. Optimization of the design by adding constrains on signals and critical paths. Timing analysis. Timing analysis. Provide a smooth transition to P&R. Provide a smooth transition to P&R. Leonardo

11. 5. Studying the Xilinx ’ s FPGA “ The Virtex II pro Family is a platform FPGA for designs that are based on IP cores and customized modules. The family incorporates multi-gigabit transceivers and PowerPC CPU cores. It empowers complete solutions for Telecommunications, Wireless, Networking, Video and DSP applications. Virtex II Pro devices are User- Programmable gate arrays with various configurable elements and embedded cores optimized for high-density and high-performance system designs. ”

12. 5. Xilinx ’ s FPGA (cont) Components: FPGA Logic: the RTL Design. FPGA Logic: the RTL Design. PowerPC MicroProcessor. PowerPC MicroProcessor. CoreConnect Bus – the Processor Local Bus (LPB). CoreConnect Bus – the Processor Local Bus (LPB). Gigabit I/O. Gigabit I/O.Functionality: Serial Transceivers Serial Transceivers (serial->parallel; parallel ->serial). (serial->parallel; parallel ->serial). PowerPC 405 RISC CPU (1 inst. Per cycle) PowerPC 405 RISC CPU (1 inst. Per cycle) I/O I/O CLB (Comb. and Sync.) – 4 slices & 2 3- state buffers CLB (Comb. and Sync.) – 4 slices & 2 3- state buffers RAM Memory RAM Memory Clock Management circuitry Clock Management circuitry (clock phase shifting, clock multiplication And division etc.)

13. 6. Studying Xilinx ’ s P&R program Synthesis stages: compileMapP & RImplement Code analysis Identification of logic structures First optimization Creating RTL View Implementation of structures Optimization Creating Technology View Placing the blocks Wiring Creating the Physical Device

14. 6. Studying Xilinx ’ s P&R program (cont.) ISE – Integrated Software Environment Xilinx design software suite. Xilinx design software suite. Various options to start the design from (HDL, EDIF). Various options to start the design from (HDL, EDIF). Quick verification of the functionality of the sources using the integrated simulation capabilities (ModelSim). Quick verification of the functionality of the sources using the integrated simulation capabilities (ModelSim). synthesis using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE (Leonardo). synthesis using the Xilinx Synthesis Technology (XST) as well as partner synthesis engines used standalone or integrated into ISE (Leonardo). The Xilinx implementation tools continue the process into a placed and routed FPGA, and finally produce a bitstream for the device configuration. The Xilinx implementation tools continue the process into a placed and routed FPGA, and finally produce a bitstream for the device configuration.

15. System View PowerPC 405 Core I-Cache D-Cache CoreConnect Processor Local Bus (PLB) User Logic External Memory High Speed Peripherals CoreConnect On-Chip Peripheral Bus (OPB) Low Speed Peripherals PLB-OPB Bridge FPGA Block RAM

16. Project Schedule Second Half of First Semester Project Schedule Second Half of First Semester 10 th week: Studying the PowerPC processor. 11 th week: Studying the EDK software for developing SoC. 12 th week: Studying the SoC design process. 13 th week: Get familiar with the Xilinx ’ s evaluation board. 14 th week: Writing and Running examples on the evaluation board.

17. Thank You