1. Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography Kwangok Jeong and Andrew B. Kahng VLSI CAD LABORATORY UC San Diego http://vlsicad.ucsd.edu/ Research supported by STARC ASP-DAC Session 5B, January 21, 2009

2. VLSI CAD LABORATORY, UCSD Motivation  Single exposure lithography  All shapes printed by one exposure  Adjacent identical features have same mean CD (critical dimension), and spatially correlated CD variations  Double patterning lithography (DPL)  Shapes are decomposed and printed in two exposures  Adjacent features can have different mean CD, and uncorrelated CD variations  New set of ‘bimodal’ challenges for timing analysis and optimization

3. VLSI CAD LABORATORY, UCSD DPL Approaches  Print lines  Misalignment  No CD difference between two adjacent lines  CD control is key factor  Print edges  Exposure difference  No CD difference between two adjacent lines  Overlay control is key factor CD variation w/o misalignment 1 st Exp./Etch 2 nd Etch 1 st Exp./Etch CD variation w/ misalignment 2 nd Etch 1 st Exp. & Etch Poly Hardmask Final patterns Resist 2 nd Exp. 1 st Exp. 2 nd Exp. 1 st Exp. 2 nd Exp. 1 st Exp. Final patterns Poly 2 nd Exp. Resist CD variation w/o misalignment CD variation w/ misalignment

4. VLSI CAD LABORATORY, UCSD Bimodal CD Distribution  Two CD distributions and Two different colorings  Two different timings  This Research  Assess potential impact of bimodal CD distribution on timing analysis and guardbanding  Cell delay and power, path delay, clock skew, path timing slack  Seek potential solutions to minimize the impact of bimodal CD distribution M 12 -type cellM 21 -type cell Gates from CD group1 Gates from CD group2

5. VLSI CAD LABORATORY, UCSD Impact on Path Delay Variation  Simulation results  Mean and sigma of a long inverter chain (16 stages) over all process corners (Min and Max combinations)  Alternately-colored paths  smaller path delay variation 16-stage 2-types Covariance worsens path delay variation  Simulation setup  45nm PTM, Typical corner (TT), 1.0V, 25 °C  16 stages of 45nm INVX4 (Nangate Open Cell Library)  Each cell can have two different colorings  Each color (Mask 1 or 2) can have two different process results (Min or Max)

6. VLSI CAD LABORATORY, UCSD Impact on Timing Slack (Analysis)  Timing slack calculation  Timing slack:  Timing slack variation:  Clock skew  Especially, clock skew from uncorrelated launching and capturing clock paths are the major source of timing slack variation.  Example Large correlation is better for timing slack Data (10  2 = 8~12ns) Clock (10  2 = 8~12ns) Worst slack = 5  5 = 0ns Worst slack = min(clock) – max(data) = 8  12 =  4ns Worst slack = 15  15 = 0ns (a)Worst slack in DPL Small delay variation but large negative slack (b) Worst slack in single exp. Large delay variation but zero slack Data (10 – 5 = 5ns) Clock (10 – 5 = 5ns) Data (10 + 5 = 15ns) Clock (10 + 5 = 15ns) BC WC

7. VLSI CAD LABORATORY, UCSD Impact on Timing Slack (Simulation Setup)  Testcase  AES from Opencores, Nangate 45nm library, PTM 45nm  Extracted critical path Clock launch: 14 stages Clock capture: 14 stages Data path: 30 stages Exhaustive tests (4 x 2 54 ) not feasible, so we fix the data path coloring. CaseLaunchCapture 1 M12+M12… 2 M21+M21… 3M12+M12…M21+M21… 4 M12+M12… 5 M12+M21… M1M2 Mean 3s Mean 3s  CD Mean Uni- modal 50.002.00-- 0nm Pooled50.002.00-- Bimodal50.002.0050.002.00 1nm Pooled50.002.50-- Bimodal49.502.0050.502.00 2nm Pooled50.003.61-- Bimodal49.002.0051.002.00 3nm Pooled50.004.92-- Bimodal48.502.0051.502.00 4nm Pooled50.006.32-- Bimodal48.002.0052.002.00 5nm Pooled50.007.76-- Bimodal47.502.0052.502.00 6nm Pooled50.009.22-- Bimodal47.002.0053.002.00

8. VLSI CAD LABORATORY, UCSD Impact on Timing Slack (Simulation Results)  Clock skew  Even for the zero mean difference case, clock skew exists and increases with mean difference  Pooled unimodal can not distinguish this clock skew  Timing slack  Originally zero slack turns out to have significant negative slack  Pooled unimodal shows very pessimistic slack 22ps 53ps Cases 1, 2, 5

9. VLSI CAD LABORATORY, UCSD Possible Solutions for Timing Optimization  Self-compensation  Alternative coloring of timing paths  reduce variation  Same coloring sequence for clock network  reduce clock skew  But: restricted coloring can increase coloring conflicts  Solutions for coloring conflicts  Candidate1: large sized cells to prevent conflicts between cells  Candidate2: Placement legalization after coloring (like UCSD *Corr) 2d pb  Res min (a) Conflict(b) No conflict 2d pb  Res min d pb d pb : distance from poly center to cell boundary Res min : minimum resolution (a) Original placement(b) Alternative coloring Coloring-fixed cells Logical connection Coloring conflict (c) Conflict Removal > Res min

10. VLSI CAD LABORATORY, UCSD Self-Compensation Is Not Enough  Self-compensation in path coloring reduces delay variation, but bimodal CD impact is still significant CD Mean Diff Rise delay (ps) Path1Path2 0n646.7 2n615.4671.3 4n587.0705.0 6n550.4736.1 CD Mean Diff Rise delay (ps) Path1Path2 0n646.7 2n630.0656.4 4n614.5674.8 6n604.6679.4 Better, but can still have timing violations

11. VLSI CAD LABORATORY, UCSD BEOL Compensation of Measured FEOL  CD  UCSD: “Design-Aware Process Adaptation”  FEOL metrology  intentional BEOL CD biasing  DPL allows wire segments in different masks to change CD independently  Color interconnects differently for different CD groups  F-factor = (in)flexibility factor for interconnect coloring, e.g., F=1, u All wire segments connected to CD_group1 gates must be in INT_MASK1 u All wire segments connected to CD_group2 gates must be in INT_MASK2

12. VLSI CAD LABORATORY, UCSD Compensation with BEOL Biasing  Small CD gates  thick interconnect (large cap.)  Large CD gates  thin interconnect (small cap.)  Example for F=0.8 (80% of interconnects colored according to the gate CD groups) CD Mean Diff Rise delay (ps) Interconnect Model Path1Path2 Nominal (nm) WidthSpace 0n646.7 0.07 2n630.0656.40.07 4n614.5674.80.07 6n604.6679.40.07 CD Mean Diff Rise delay (ps) Interconnect Model (biasing) Path1Path2 INT1 (80%) INT2 (20%) Space Width 0n 646.7 0.07 2n 618.2646.70.0710.0630.073 4n 601.6646.70.0720.0580.075 6n 585.1652.30.0750.0530.076 meet timing Change metal/ILD thickness?

13. VLSI CAD LABORATORY, UCSD Conclusions  Analytical and empirical assessments of DPL potential impact on timing analysis error and design guardband  Traditional ‘unimodal’ analysis may not be viable for DPL  Our analysis: 20% or greater change in timing  Self-compensation strategies, along with BEOL biasing, can reduce impact of bimodal CD variation  Work at UCSD: “Design-Aware Process Adaptation”  Ongoing work: more accurate, efficient and practical solutions to ‘bimodal-awareness’ challenges in timing analysis and circuit optimization

14. BACKUP

15. VLSI CAD LABORATORY, UCSD Impact on Cell Delay and Power  Monte Carlo simulations : #10K  DPL1: (2n-1)-th gate is group1 and 2n-th gate is group2  DPL2: 2n-th gate is group1 and (2n-1)-th gate is group2  Unimodal: CD distribution covers CD group1  CD group2  Unimodal representation is too pessimistic  Characteristics of DPL1 and DPL2 are very different! rise fall rise fall Input 1 Input 0 Input 1 Input 0 60 59 54 61 Bimodal group1 Bimodal group2 Worst CDBest CD Unimodal 56 6466 2n

16. VLSI CAD LABORATORY, UCSD Impact on Design Guardband  Comparison of required design guardband  Unimodal approximation: conservative but easy  Lead to over-design  But can use conventional flow  Bimodal-aware: realistic but complex method  New bimodal-aware timing analysis and new timing-driven design optimizations are required