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Power Delivery Challenges for High Performance Low Voltage Microprocessors Tanay Karnik Microprocessor Research Labs Intel Corporation November 9, 2001
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Extrapolating Moore’s Law
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Making Moore’s Law Work
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& power will limit performance
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Energy Requirement More energy reduction initiatives required in future
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Ldi/dt getting worse Package L needs to reduce S -3Package L needs to reduce S -3 Various Sources of Resonance Package L – Die CPackage L – Die C Socket L – Package CSocket L – Package C Motherboard L – Socket CMotherboard L – Socket C Parasitic Inductance Unknown Return Paths Simple layouts form loops which inadvertently interact via magnetic fields
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Supply currents reduce only linearly with voltage. –Power Density to increase Surpassed hot-plate power density in 0.6u (P6)Surpassed hot-plate power density in 0.6u (P6) Junction Temp need to work with package research)Junction Temp need to work with package research) Expect parasitics to increase –Capacitance will increase –R may reduce, but not much –L’s will not reduce Noise will increase –RI drops in power distribution –L(di/dt) noise will increase S/N will reduce Die Power Delivery CHALLENGE: DELIVER 150A AT 0.9V COST EFFECTIVELY
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Larger temperature gradient requires smaller heat sink and air flow rate for dissipating the same power. Reduction in ja will increase cooling cost rapidly. Maintaining larger die temperature reduces ja in an active power dominated technology. In leakage power dominated technologies larger T j will impact P w and hence ja and cooling cost. Cooling cost
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Present Data CPU consumes 55% Platform Power Single 300-watt or 1+1 350-watt redundant power supply configuration for Intel serversSingle 300-watt or 1+1 350-watt redundant power supply configuration for Intel servers 15A/100V industrial server requirement Future Directions Paradigm Shifting: Move Bulk DC/DC Conversion and Redundancy into the Rack Increase the Density Of Power Conversion Everywhere Integrate Power, Mechanical and Thermal Functions Integrate the Design of Air movers and the System Server/Platform Level Challenges
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Possible VRM Solutions Board VRM close to μP load with low impedance interconnect On-Package Switched DC/DC Convertors On-Die DC/DC Convertors
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Power/Thermal Integration Integrated Power Delivery & Thermal
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Summary The power challenges for next generation microprocessors require an Integrated Approach Optimum Power delivery requires VRM as close as possible to the load of the microprocessor Thorough analysis of entire power interconnect path is a must High density power delivery => High cost cooling
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