1. Copyright Agrawal & Srivaths, 2007 Low-Power Design and Test, Lecture 5 1 Low-Power Design and Test Gate-Level Power Optimization Vishwani D. Agrawal Auburn University, USA vagrawal@eng.auburn.edu Srivaths Ravi Texas Instruments India Srivaths.ravi@ti.com Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html

2. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 52 Components of Power  Dynamic  Signal transitions  Logic activity  Glitches  Short-circuit  Static  Leakage

3. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 53 Power of a Transition V DD Ground CLCL R R Dynamic Power = C L V DD 2 /2 + P sc ViVi VoVo i sc

4. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 54 Dynamic Power  Each transition of a gate consumes CV 2 /2.  Methods of power saving:  Minimize load capacitances  Transistor sizing  Library-based gate selection  Reduce transitions  Logic design  Glitch reduction

5. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 55 Glitch Power Reduction  Design a digital circuit for minimum transient energy consumption by eliminating hazards

6. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 56 Theorem 1  For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. Output logic state changes One transition is necessary Output logic state unchanged No transition is necessary

7. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 57 Event Propagation 2 4 6 1 1 3 5 3 1 0 0 0 2 2 Path P1 P2 Path P3 Single lumped inertial delay modeled for each gate PI transitions assumed to occur without time skew

8. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 58 Inertial Delay of an Inverter d HL d LH d HL +d LH d = ──── 2 V in V out time

9. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 59 Multi-Input Gate Delay = d ABAB C ABCABC d dHazard or glitch DPD DPD: Differential path delay

10. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 510 Balanced Path Delays Delay = d ABAB C ABCABC d No glitch DPD Delay buffer

11. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 511 Glitch Filtering by Inertia Delay ≥ DPD ABAB C ABCABC d =DPD Filtered glitch DPD

12. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 512  Given that events occur at the input of a gate with inertial delay d at times, t 1 ≤... ≤ t n, the number of events at the gate output cannot exceed Theorem 2 min ( n, 1 + ) t n – t 1 --------d t n - t 1 t n - t 1 t 1 t 2 t 3 t n t 1 t 2 t 3 t n time time

13. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 513 Minimum Transient Design  Minimum transient energy condition for a Boolean gate: | t i - t j | < d Where t i and t j are arrival times of input events and d is the inertial delay of gate

14. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 514 Balanced Delay Method  All input events arrive simultaneously  Overall circuit delay not increased  Delay buffers may have to be inserted 1 1 1 1 1 1 1 1 3 1 1 No increase in critical path delay

15. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 515 Hazard Filter Method  Gate delay is made greater than maximum input path delay difference  No delay buffers needed (least transient energy)  Overall circuit delay may increase 1 1 1 1 1 3 1 1 1 1

16. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 516 Designing a Glitch-Free Circuit  Maintain specified critical path delay.  Glitch suppressed at all gates by  Path delay balancing  Glitch filtering by increasing inertial delay of gates  A linear program optimally combines all objectives. D Delay = d1 Delay = d2 |d1 – d2| < D

17. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 517 Benchmark Circuits Circuit ALU4 C880 C6288 c7552 Max-delay (gates) 7 15 24 48 47 94 43 86 No. of Buffers 5 0 62 34 294 120 366 111 Average 0.80 0.79 0.68 0.40 0.36 0.44 0.42 Peak 0.68 0.67 0.54 0.52 0.36 0.34 0.32 Normalized Power

18. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 518 Four-Bit ALU maxdelay Buffers inserted 75 102 121 150 Maximum Power Savings (zero-buffer design): Peak = 33 %, Average = 21 %

19. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 519 ALU4: Original and Low-Power

20. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 520 C7552 Circuit: Spice Simulation Power Saving: Average 58%, Peak 68%

21. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 521 References  R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993.  M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183- 188.  V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10 th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197.  V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12 th Int’l Conf. VLSI Design, Jan. 1999, pp. 434-439.  M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51.  T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16 th Int’l Conf. VLSI Design, Jan. 2003, pp. 527-532.  T. Raja, V. D. Agrawal and M. L. Bushnell, “Variable Input Delay CMOS Logic for Low Power Design,” Proc. 18 th Int’l Conf. VLSI Design, Jan. 2005, pp. 596-603.

22. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 522 Components of Power  Dynamic  Signal transitions  Logic activity  Glitches  Short-circuit  Static  Leakage

23. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 523 Subthreshold Conduction V gs – V th -V ds I ds =I 0 exp( ───── ) × (1– exp ── ) nV T V T Sunthreshold slope 0 0.3 0.6 0.9 1.2 1.5 1.8 V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA V th Subthreshold region Saturation region

24. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 524 Thermal Voltage, v T V T = kT/q = 26 mV, at room temperature. When V ds is several times greater than V T V gs – V th I ds =I 0 exp( ───── ) nV T

25. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 525 Leakage Current  Leakage current equals I ds when V gs = 0  Leakage current, I ds = I 0 exp(-V th /nV T )  At cutoff, V gs = V th, and I ds = I 0  Lowering leakage to 10 -b I 0 V th = bnV T ln 10 = 1.5b × 26 ln 10 = 90b mV  Example: To lower leakage to I 0 /1,000 V th = 270 mV

26. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 526 Threshold Voltage  V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ]  V t0 is threshold voltage when source is at body potential (0.4 V for 180nm process)  Φ s = 2V T ln(N A /n i ) is surface potential  γ = (2qε si N A ) ½ t ox /ε ox is body effect coefficient (0.4 to 1.0)  N A is doping level = 8×10 17 cm -3  n i = 1.45×10 10 cm -3

27. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 527 Threshold Voltage, V sb = 1.1V  Thermal voltage, V T = kT/q = 26 mV  Φ s = 0.93 V  ε ox = 3.9×8.85×10 -14 F/cm  ε si = 11.7×8.85×10 -14 F/cm  t ox = 40 A o  γ = 0.6 V ½  V th = V t0 + γ[(Φ s +V sb ) ½ - Φ s ½ ] = 0.68 V

28. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 528 A Sample Calculation  V DD = 1.2V, 100nm CMOS process  Transistor width, W = 0.5μm  OFF device (V gs = V th ) leakage  I 0 = 20nA/μm, for low threshold transistor  I 0 = 3nA/μm, for high threshold transistor  100M transistor chip  Power = (100×10 6 /2)(0.5×20×10 -9 A)(1.2V) = 600mW for all low-threshold transistors  Power = (100×10 6 /2)(0.5×3×10 -9 A)(1.2V) = 90mW for all high-threshold transistors

29. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 529 Dual-Threshold Chip  Low-threshold only for 20% transistors on critical path.  Leakage power = 600×0.2 + 90×0.8 = 120 + 72 = 192 mW

30. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 530 Dual-Threshold CMOS Circuit

31. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 531 Dual-Threshold Design  To maintain performance, all gates on the critical path are assigned low V th.  Most of the other gates are assigned high V th. But,  Some gates on non-critical paths may also be assigned low V th to prevent those paths from becoming critical.

32. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 532 Integer Linear Programming (ILP) to Minimize Leakage Power  Use dual-threshold CMOS process  First, assign all gates low V th  Use an ILP model to find the delay (T c ) of the critical path  Use another ILP model to find the optimal V th assignment as well as the reduced leakage power for all gates without increasing T c  Further reduction of leakage power possible by letting T c increase

33. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 533 ILP -Variables For each gate i define two variables.  T i : the longest time at which the output of gate i can produce an event after the occurrence of an input event at a primary input of the circuit.  X i : a variable specifying low or high V th for gate i ; X i is an integer [0, 1], 1  gate i is assigned low V th, 1  gate i is assigned low V th, 0  gate i is assigned high V th.

34. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 534 ILP - objective function minimize the sum of all gate leakage currents, given by  I Li is the leakage current of gate i with low V th  I Hi is the leakage current of gate i with high V th  Using SPICE simulation results, construct a leakage current look up table, which is indexed by the gate type and the input vector. Leakage power:

35. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 535 ILP - Constraints  For each gate (1) (1) output of gate j is fanin of gate i (2) (2)  Max delay constraints for primary outputs (PO) (3) T max is the maximum delay of the critical path Gate j Gate i TjTj TiTi

36. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 536 ILP Constraint Example  Assume all primary input (PI) signals on the left arrive at the same time.  For gate 2, constraints are

37. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 537 ILP – Constraints (cont.)  D Hi is the delay of gate i with high V th  D Li is the delay of gate i with low V th  A second look-up table is constructed and specifies the delay for given gate type and fanout number.

38. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 538 ILP – Finding Critical Delay  T max can be specified or be the delay of longest path (T c ).  To find T c, we change constraints (2) to an equation, assigning all gates low V th  Maximum T i in the ILP solution is T c.  If we replace T max with T c, the objective function minimizes leakage power without sacrificing performance.

39. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 539 Power-Delay Tradeoff

40. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 540 Power-Delay Tradeoff  If we gradually increase T max from T c, leakage power is further reduced, because more gates can be assigned high V th.  But, the reduction trends to become slower.  When T max = (130%) T c, the reduction about levels off because almost all gates are assigned high V th.  Maximum leakage reduction can be 98%.

41. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 541 Leakage & Dynamic Power Optimization 70nm CMOS c7552 Benchmark Circuit @ 90 o C Leakage exceeds dynamic power Y. Lu and V. D. Agrawal, “CMOS Leakage and Glitch Minimization for Power- Performance Tradeoff,” Journal of Low Power Electronics (JOLPE), vol. 2, no. 3, pp. 378- 387, December 2006.

42. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 542 Summary  Leakage power is a significant fraction of the total power in nanometer CMOS devices.  Leakage power increases with temperature; can be as much as dynamic power.  Dual threshold design can reduce leakage.  Reference: Y. Lu and V. D. Agrawal, “ CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff, ” J. Low Power Electronics, Vol. 2, No. 3, pp. 378-387, December 2006.  Access other paper at http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html http://www.eng.auburn.edu/~vagrawal/TALKS/talks.html

43. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 543 Problem: Leakage Reduction Following circuit is designed in 65nm CMOS technology using low threshold transistors. Each gate has a delay of 5ps and a leakage current of 10nA. Given that a gate with high threshold transistors has a delay of 12ps and leakage of 1nA, optimally design the circuit with dual-threshold gates to minimize the leakage current without increasing the critical path delay. What is the percentage reduction in leakage power? What will the leakage power reduction be if a 30% increase in the critical path delay is allowed?

44. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 544 Solution 1: No Delay Increase Three critical paths are from the first, second and third inputs to the last output, shown by a dashed line arrow. Each has five gates and a delay of 25ps. None of the five gates on the critical path (red arrow) can be assigned a high threshold. Also, the two inverters that are on four-gate long paths cannot be assigned high threshold because then the delay of those paths will become 27ps. The remaining three inverters and the NOR gate can be assigned high threshold. These gates are shaded grey in the circuit. The reduction in leakage power = 1 – (4×1+7×10)/(11×10) = 32.73% Critical path delay = 25ps

45. Copyright Agrawal & Srivaths, 2007Low-Power Design and Test, Lecture 545 Solution 2: 30% Delay Increase Several solutions are possible. Notice that any 3-gate path can have 2 high threshold gates. Four and five gate paths can have only one high threshold gate. One solution is shown in the figure below where six high threshold gates are shown with shading and the critical path is shown by a dashed red line arrow. The reduction in leakage power = 1 – (6×1+5×10)/(11×10) = 49.09% Critical path delay = 29ps