1. 4 Bit Serial to Parallel Data Stream Converter Vinaya Anne Kristy Lypen Michael Scheel Victor Zavaleta Vinaya Anne Kristy Lypen Michael Scheel Victor Zavaleta

2. Design Specifications  Convert a serial data stream every 4 clock cycles to a 4 bit parallel stream  Operate at the positive edge of the clock  Drive a 10pF load at 25MHz  Minimize skew  Area less than 40mil 2

3. Parameters  D Flip-Flop Wn Caclulated = 10.4  m Wn Actual = 23.2  m Wp Caclulated = 27.6  m Wp Actual = 27.6  m Based on C Load of Output = 179f F  Buffer  Total Area: 1750 x 600  m Power: 400mW Stage Wp (  m)Wn (  m) One300100 Two8028.8 Three25.29.2

4. Block Diagram Schmidt Trigger Frequency Counter SERIALSERIAL D Flip Flop D Flip Flop D Flip Flop Latch / Buffer DATADATA PARALLELPARALLEL DATADATA

5. Schmidt Trigger Schematic

6. Trip Points of Schmidt Trigger

7. D Flip-Flop Schematic

8. D Flip-Flop Propagation Delay Waveform

9. Schematic D Flip-Flop / Logic Circuit

10. Output Waveforms

11. Layout of Four D Flip-Flops

12. Clock

13. Buffer Schematic

14. Buffer Transient Response

15. Questions?