1. Spring 08, Feb 26 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2008 Clock Skew Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html

2. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)2 Single Clock FF AFF B Comb. CK Data_in Data_out CKA CKB Single-cycle path delay

3. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)3 Multiple Clocks FF AFF B Comb. Data_in Data_out CKA CKB Multi-cycle path delay

4. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)4 Clock Skew  Skew is the time delay of clock signal at a flip- flop with respect to some time reference.  For a given layout each flip-flop has a skew, measured with respect to the a common reference.  Skews of flip-flops separated by combinational paths affect the short-path and long-path constraints.

5. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)5 Skews for Single-Cycle Paths Combinational Block Delay: FFi CKi FFj CKj xixj xi and xj are arrival times of clock edges δ(i,j) ≤ d(i,j) ≤ Δ(i,j)

6. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)6 Short-Path Constraint (Double-Clocking) CKi CKj xi xj intended Not intended Thj xi + δ(i,j) ≥ xj + Thj δ(i,j) Tck

7. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)7 Long-Path Constraint (Zero-Clocking) CKj CKi xi xj intended Not intended Tsj xi + Δ(i,j) ≤ xj + Tck – Tsj Δ(i,j) Tck

8. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)8 Maximum Clock Frequency Linear program: Minimize Tck Subject to: For all flip-flop pairs (i,j), xi + δ(i,j) ≥ xj + Thj xi + Δ(i,j) ≤ xj + Tck – Tsj

9. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)9 Finding Clock Skews FFi Ci Ri FFj Cj Rj FFk Ck Rk CK xi xj xk Use Elmore delay formula to calculate xi, xj, xk.

10. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)10 Interconnect Delay: Elmore Delay Model  W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. CK i j k Ri Rj Rk Ci Cj Ck Shared resistance: Rii = Ri Rij = Rji = Ri Rik = Rki = Ri Rjj = Ri + Rj Rjk = Rkj = Ri + Rj Rkk = Ri + Rj + Rk

11. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)11 Elmore Delay Calculation Delay at node k, xk= 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk ) = 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]

12. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)12 Finding δ(I,j) and Δ(I,j) A1A1 B3B3 C1C1 D2D2 E1E1 F1F1 J1J1 G2G2 H3H3 , -  0, 0 , -  i j k 3, 3 , -  4, 4 5, 5 6, 7 6, 8 , -  9, 10 Minimum delay Maximum delay

13. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)13 Maximum Clock Frequency for Tolerance ±q/2 in Skew Linear program:Minimize Tck Subject to:For all flip-flop pairs (i,j), xi + δ(i,j) ≥ xj + Thj + q xi + Δ(i,j) ≤ xj + Tck – Tsj – q Where q is a constant xi are variables, ximin ≤ xi Tck is a variable

14. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)14 Maximum Tolerance for Given Clock Frequency Linear program:Maximize q Subject to:For all flip-flop pairs (i,j), xi + δ(i,j) ≥ xj + Thj + q xi + Δ(i,j) ≤ xj + Tck – Tsj – q Where Tck is a constant xi are variables, ximin ≤ xi q is a variable

15. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)15 Tradeoffs Increasing clock period Tck Increasing skew tolerance q No solution because of zero slack.

16. Spring 08, Feb 26ELEC 7770: Advanced VLSI Design (Agrawal)16 Clock Skew Problem   N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.  J. P. Fishburn, “Clock Skew Optimization,” IEEE Trans. Computers, vol. 39, no. 7, pp. 945-951, July 1990.