1. Computer Architecture: Intro Beginnings J. Schmalzel S. Mandayam

2. Course §Introduction §Overview §Content launch: Module 1

3. Structure & Conduct of the Course §Discussion v. Lecturing §Interaction: Question/Comment Ticket §Team-learning §In-class labs §Out-of-class labs, readings, problems

4. Introduction §Instructors: J. Schmalzel, S. Mandayam §Course l Digital Foundations l Introduction to Embedded Processors l The Embedded Development Environment l Interfacing to the Physical World l Hardware and Software Trade-Offs

5. Course Goal §Goal: Impart knowledge of computer architecture to support informed decisions about the hardware, software, and the hardware/software trade-offs that underlie the computing paradigm.

6. Objectives, 1  Describe major functional elements of CISC, RISC architectures  Perform detailed analysis and synthesis of combinatorial and sequential subsystems using schematic and/or behavioral design capture w/ sim  Describe principles and applications of the three basic computing elements: CPU, MEM, I/O  Use an embedded system that includes diverse architectural features

7. Objectives, 2  Apply analytic and simulation techniques to predict and verify performance metrics  Design an example architecture using SOTA tools  Identify opportunities for hardware and software trade-offs  (Insert your objectives here…)  ( …and here)

8. Digital Foundations §The basic model of a computer system: CPUMEM I/O

9. Central Processing Unit (CPU) §Controls §Executes §Computes (Fixed- and/or Floating- Point)

10. Memory §Program store §Data storage §High-speed  Low-speed §Volatile, Non-volatile l RAM, ROM, FLASH (EEPROM) §Fast  Slow

11. Input/Output (I/O) §Communication between CPU and outside world §Fast  Slow §Standardized (e.g., IEEE 802.11b) §Parallel (IEEE 1184)  Serial (USB 2.0)

12. Hierarchical View of EP and Digital Systems CPUMEM I/O Gates Boolean Algebra Design Techniques MSI Functions State Machines Interface Method Computer Architecture Operating System HLLs

13. Number Systems l Binary l Hexadecimal l Octal

14. For an n-bit binary number : Base notation. For a k-bit binary number with n-bits to the left of the radix point and m-bits to the right of the radix point. For example, 1101001.101 = ______________ 10 = (64 + 32 + 8 + 1). (0.5 + 0.125) = 105.625 Similarly, for hex:

15. Conversions 11111111  ____________(10) (Fast way: 100000000 -1 = 255) 10101010.01  _____________ (10) (AA.4 16 = 10*16 + 10 +.25 = 170.25) AB6C.D  _________________________ (2)  ___________(10) (1010101101101100.1101; 10*4096 + 11*256 + 6*16 + 12 + 13/16 = 43,884.8125)

16. Coding Binary system must be used to accomplish many functions such as arithmetic and data transmission. A code defines the mapping between binary digits and the intended application.

17. Example Codes §Gray code: Only one bit change between adjacent codes (000  010  110  100  101  111  011  001  000…) §Binary-Coded Decimal (BCD): Direct (but inefficient) coding of decimal numbers using 4 bits

18. 2’s Complement Need: A method to represent negative numbers. Can use a sign bit + magnitude; e.g., +5: 0 101, -5: 1 101, but there are better codes. The 2’s Complement is one. 1’s Complement: Complement each bit. 1’s Complement of 11011 is 00100 2’s complement: 1’s complement + 1 Example: Find 2’s complement of 1001100.  _______________ (0110100.) To check, sum of the positive and negative codes should sum to zero (ignore overflow out of msb). (“By inspection” trick: Working from right to left, write down all zeros until the first 1. Write it down, too, then complement every bit after that.)

19. Boolean Algebra §True/False l High/Low l On/Off l +5 Vdc / 0 Vdc (+3.3 Vdc / 0 Vdc) §Notation l Variable by itself is assumed “true” l Variable with a symbol denotes complementation: ¯ ~ * /

20. Boolean Identities §X  0=0 §X  1=X §X  X=X §X  X*=0 §X+0=X §X+1=1 §X+X=X §X+X*=1 §X**=X §Commutative Laws: X+Y=Y+X XY=YX §Associative Laws: X+(Y+Z)=(X+Y)+Z X(YZ)=(XY)Z §Distributive Laws: X(Y+Z)=XY+XZ §DeMorgan’s Theorems: (X  Y)*=X*+Y* (X+Y)*=X*  Y*

21. Gates (p. 63 M&K) AND ( ^ & C: & ) OR (  + C: | ) NOT {Inverter} ( ¯ ~ * / C: ~ ) XOR (  C:  ) NAND NOR XNOR

22. Combinatorial Design Process §Problem statement §Truth table and describing Boolean Algebra §Simplification §Implementation §Verification

23. Design Examples §Full Adder (Step 1: Design a device that performs binary addition, including carry input.) FA A B Ci S Co

24. Full Adder Truth Table (Step 2) 0 0 00 0 Ci A BS Co 0 0 11 0 0 1 01 0 0 1 10 1 1 0 01 0 1 0 10 1 1 1 00 1 1 1 11 1 Sum-of-Product Boolean expressions for S and Co: S = Ci*A*B + Ci*AB* + CiA*B* + CiAB Co = Ci*AB + CiA*B + CiAB* + CiAB

25. Graphical Simplification (Step 3) 01 0 1 00 01 11 10 Co 0 00 1 11 Ci AB BCi AB ACi Co = AB + ACi + BCi A Karnaugh-Map organizes truth table entries as a gray code--only one variable changes between adjacent cells. This lets you use the identities X+X*=1 and X*1=X to simplify by inspection. For example, the AB subcube: ABCi* + ABCi = AB(Ci*+Ci) = AB(1) = AB

26. Other Simplification Methods §Quine-McCluskey algorithm “Espresso” http://www-cad.eecs.berkeley.edu:80/Software/software.html http://cse.bellarmine.edu/espresso (C. Staley; Find it on download.com)

27. Espresso Demo Simplify So and Co for FA

28. Implementation (Step 3) Translate the simplified BA to a network of gates: & & & + Ci A B A B Co

29. Verification (Step 4) Verify the proper behavior of the design. Use simulation techniques to present test vectors and compare responses to predictions. Exhaustivev.Statistical (Monte Carlo)

30. Combinatorial Function Blocks §Decoders §Multiplexers

31. Digital Foundations, cont. §The basic model of a computer system: CPUMEM I/O

32. Real Gates §Logic levels are voltage levels §Finite current drive §Timing diagrams §Finite switching speed §Propagation delays §Noise

33. Logic Levels are Voltage Levels Vdd Vss High Low V OH min V OL max V IL max V IH min V OH typ V OL typ

34. Finite Current Levels V OH ’/V OL ’ + RSRS V OH /V OL The electrical circuit model for a digital output (or input) includes a series impedance. This helps explain why a gate can’t source/sink unlimited amounts of current (mA v. A).

35. Finite Switching Speeds Example: Switching speed of an inverter. A timing diagram shows behavior as it develops with time. Input (Ideal) Output trtr tftf

36. Finite Propagation Delays Example: Switching speed of an inverter. Input (Ideal) Output t PD LH t PD HL

37. Noise How well logic is able to reject noise is described by its Noise Immunity. The Noise Margin (NM) is the predicted ability of a device to handle noise on its inputs and still reliably determine the correct logic levels. NM L = V OLmax - V ILmax NM H = V OHmin - V IHmin

38. Logic Levels/Voltage Levels for 74HC138 w/ VCC=5 Vdc Vdd Vss High Low V OH min V OL max V IL max V IH min V OH typ V OL typ 3.5 V (0.7*5.0) 1.5 V (0.3*5.0) 4.9 V (5.0-0.1) 4.999 @I OH = -20  A 0.1 V (0.0+0.1) 0.001 @I OL = +20  A

39. Variation in V OH and V OL V OH or V OL I OH I OL This is reference direction--that’s why I OH is negative. Ideal V OH or V OL + RsRs What is a typical Rs?

40. Calculation of Rs at I OL of 4 mA V OH or V OL I OH I OL This is reference direction--that’s why I OH is negative. Ideal V OH or V OL + RsRs Use 6 Vdc values: 0.26V/.004A = 65 

41. Propagation delay (6 Vdc) §From A, B, or C to any Y output: Max 38 ns §From Enable to any Y output: Max 33 ns

42. Questions, Comments, Discussion