1. Chapters 4 & 5: LC-3 Computer Architecture Machine Instructions Assembly language Programming in Machine and Assembly Language

2. Overview The LC-3 Computer 16 bit machine, word addressable, 64K or 65,536 locations Computer Machine Instructions – Computer “native” instructions - The basic instructions that all programs use on that computer (The “atomic” unit of work done by a computer) The Instruction Cycle - The steps in the execution of a machine language instruction (Fetch, Decode, Evaluate Address(es), Fetch operand(s), Execute, and Store results)

3. LC-3 Data Path: Combinational Logic State Machine Storage

4. Data Path of the LC-3

5. LC-3 Memory Layout x0000 – x2FFF System: Operating System programs, tables, and data - Generally off limits to programmer (Programs run in Supervisor mode) x3000 – xFDFF User: User Program and Data Area Area shared by users like you (Nominally run in non-supervisor mode) xFE00 – xFFFF Device: I/O Register Addresses Pseudo memory used for input/output R0-R7 Registers (16 bit)

6. LC-3 Memory Map

7. Computer Machine Instruction Formats What is IN an instruction? Operation code – what to do Input Operand(s) – where to get input operands (memory, registers) Output Operand(s) – Where to put results (memory, registers) What are the major instruction types? Data Movement (load, store, etc.) Operate (add, sub, mult,OR, AND, etc.) Control (branch, jump to subroutine, etc.)

8. The Instruction Cycle Steps (or phases): Fetch Next Instruction from Memory (PC)  (points to) next instruction PC  ( PC) + 1 Decode Fetched Instruction Evaluate Address (es) (find where the data is) Fetch Operand (s) (get data) Execute Operation Store Result (if specified)

9. The LC-3 Instruction Addressing Modes Register (Operand is in one of the 8 registers) PC-relative (Operand is “offset” from the (PC) ) Base + Offset (Base relative) (Operand is “offset” from the contents of a register) Immediate (Operand is in the instruction) Indirect (The “Operand” actually points to the real address – rather than being the operand)

10. The LC-3 Instruction Addressing Modes Register (Operand is in one of the 8 registers) Immediate (Operand is in the instruction) PC-relative (Operand is “offset” from the (PC) ) Indirect (The “Operand” actually points to the real address – rather than being the operand) Base + Offset (Base relative) (Operand is “offset” from the contents of a register) Note: no Direct Addressing defined in the LC-3

11. LC-3 Instructions (Fig 5.3 – Appendix a)

12. Operate Instructions Only three operations: ADD, AND, NOT Source and Destination operands are: Registers

13. ADD/AND (Register)

14. NOT (Register) Note: Src and Dst could be the same register.

15. ADD/AND (Immediate) Note: Immediate field is sign-extended.

16. Data Movement Instructions Load -- read data from memory to register –LD: PC-relative mode [0010 DR PCoffset9] –LDI: indirect mode [1010 DR PCoffset9] –LDR: base+offset mode[0110 DR BaseR offset6] Store -- write data from register to memory –ST: PC-relative mode[0011 DR PCoffset9] –STI: indirect mode [1011 DR PCoffset9] –STR: base+offset mode [0111 DR BaseR offset6] Load effective address – address saved in register –LEA: immediate mode[1110 DR PCoffset9]

17. LD (PC-Relative)

18. ST (PC-Relative)

19. LDI (Indirect)

20. STI (Indirect)

21. LDR (Base+Offset)

22. STR (Base+Offset)

23. LEA (Immediate)

24. Branch Instruction BR [0000 nzp PCoffset9] Branch specifies one or more condition codes If the set bit is specified, the branch is taken: –PC is set to the address specified in the instruction –Target address is made by adding SEXT(IR[8:0]) to the PC If the branch is not taken: - the next sequential instruction (PC) is executed.

25. BR ///////////// /////+ SEXT

26. Jump Instruction JMP BaseR [1100 000 BaseR 000000] Jump is an unconditional branch -- always taken. Base –Address is contents of the register –Allows any target address.

27. TRAP Calls a service routine, identified by 8-bit “trap vector.” When routine is done, PC is set to the instruction following TRAP. vectorroutine x23input a character from the keyboard x21output a character to the monitor x25halt the program

28. TRAPS

29. Using Branch Instructions Compute sum of 12 integers. Numbers start at location x3100. Program starts at location x3000. R1  x3100 R3  0 R2  12 R2=0? R4  M[R1] R3  R3+R4 R1  R1+1 R2  R2-1 NO YES R3: Accumulator for the sum of integers R1: Array index pointer (Begin with location 3100) R4: Temporary register to store next integer R2: Loop counter (Count down from 12)

30. Sample Program AddressInstructionComments x30001 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1  x3100 (PC+0xFF) x30010 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 R3  0 x30020 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0 x30030 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 R2  12 x30040 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1If Z, goto x300A (PC+5) x30050 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0Load next value to R4 x30060 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1Add to R3 x30070 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1Increment R1 (pointer) X30080 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1Decrement R2 (counter) x30090 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0Goto x3004 (PC-6)

31. Example 1: Multiply This program multiplies two unsigned integers in R4 and R5. x3200 0101010010100000 x3201 0001010010000100 x3202 0001101101111111 x3203 0000011111111101 x3204 1111000000100101 clear R2 add R4 to R2 decrement R5 R5 = 0? HALT No Yes R2 <- 0 R2 <- R2 + R4 R5 <- R5 – 1 BRzp x3201 HALT