1. Circuit Characterization Feb 4, 2005

2. Basic Device Equations (p.51)  Cutoff region: V gs  V t  I ds = 0  Linear/non-saturation region: 0<V ds <V gs -V t  I ds =  ((V gs – V t )V ds – V ds 2 /2)  Due to –V ds 2 /2, it is not really linear unless is V ds very small  Saturation region: 0<V gs – V t <V ds  I ds =  (V gs – V t ) 2 /2

3. Terms  I ds is drain-to-source current  V ds is drain-to-source voltage  V gs is gate-to-source voltage  V t is threshold voltage   is MOS transistor gain factor   =(  /t ox )(W/L), where  is carrier mobility,  is gate oxide permittivity, t ox is thickness of gate oxide, W and L are gate width and length  Example on p. 53

4. Importance of Interconnect  Interconnect delay dominates gate delay delay (ps) technology

5. Wire Resistance  Basic formula R=(  /t)(l/w)   : resistivity  t: thickness, fixed for a given technology and layer number  l: conductor length  w: conductor witdh t l w

6. Sheet Resistance  Simply R=(  /t)(l/w)=R s (l/w)  R s : sheet resistance Ohms/square, where t is the metal thickness for that metal layer  l: conductor length  w: conductor witdh l w

7. Typical Rs (Ohm/sq) MinTypicalMax M1, M20.050.070.1 M3, M40.030.040.05 Poly152030 Silicide236 Diffusio n 1025100 N-well100020005000

8. Compute Resistance  Partition long wire into rectangles  Count the number of squares ((l 1 /w 1 )+(l 2 /w 2 )+(l 3 /w 3 ))R s w1w1 l1l1 w2w2 l2l2 l3l3 w3w3

9. More Accurate Method w2w2 w1w1 Ratio=w 1 /w 2 RatioRs 12.5 1.52.55 22.6 32.75 w1w1 w2w2 RatioRs 1.52.1 22.25 32.5 42.65

10. Contact and Via  Fixed resistance for each type of contact and via  0.25 ohm to 10 ohms  Could vary due to process variation

11. Capacitor  A capacitor is a device that can store an electric charge by applying a voltage  The capacitance is measured by the ratio of the charge stored to the applied voltage  Capacitance is measured in Farads

12. 3D Parasitic Capacitance  Given a set of conductors, compute the capacitance between all pairs of conductors. - - - - - - - + + + + + C=Q/V 1V

13. 2D Simplified Model  Area capacitance: area overlap between adjacent layers  Coupling capacitance: between side-walls on the same layer  Fringing capacitance: between side-wall and adjacent layers m2 m1 m3

14. Wire Capacitance  More difficult due to multiple layers, different dielectric, void, and conformal m1 m3 m2 m1 m3  =3.9  =8.0  =4.0  =4.1 void conformal multiple dielectric

15. 2D Method  C = Ca*(overlap area) +Cc*(length of parallel run) +Cf*(perimeter)  Coefficients Ca, Cc and Cf are given by the fab  Cadence Dracula  Fast but inaccurate

16. 2.5D Method  Consider interaction between layer i and layers i+1, i+2, i–1 and i–2  Consider distance between conductors on the same layer  Cadence Silicon Ensemble  Accuracy  50%

17. Library Based Methods  Build a library of tens of thousands of patterns and compute capacitance for each pattern  Partition layout into blocks, and match with the library  Accuracy  20%

18. 3D Methods  Finite difference/finite element method  Most accurate, slowest  Raphael  Boundary element method  FastCap, Hicap  Monte Carlo random walk  QuickCap