1. הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Virtex II-PRO Dynamical Test Application Performed By: Luba Khaskin Raziel Einhorn Instructor: Ina Rivkin Spring 2004

2. Table of contents ● Background - Space Compatibility ● The General System ● Test Environment ● Testing techniques ● Design tools ● Schedule

3. Background-Space Compatibility ●In space, electronic modules are exposed to great amount of radiation causing various errors. ●As for today, space-compatible devices are being manufactured in a separated procedure, which is more expensive and complicated than the one being used for non-space (civilian) devices. ●As always, the goal is to reduce satellites’ costs. Therefore, one of the ways will be examining possible space-compatibility of civilian devices, in order to integrate them in the satellites.

4. ●The system module being examined is the Xilinx Virtex II-Pro. ●In previous project, the V2P was examined statically: testing the device’s functionality before and after radiating it. ●In this project, following the previous one, we will examine ways to test its functionality dynamically: under real-time radiation conditions similar to those in space. ●We will concentrate in examining the device’s robustness to temporary damage and it’s ability to recover in a case of an error.

5. The General System Errors MONITOR t DUT (process) radiation

6. DUT Virtex II-Pro Evaluation Board (platform) Host JTAG PortSerial Port Outputs (Leds, LCD)Input (DIP Switches, Push Buttons) Test Environment Xilinx Tools GUI Hyper Terminal LogicPower PC

7. HOST - Upper layer - GUI  User interface for determining test modes  Operating transparency – no previous VHDL knowledge required  Loading and running the tests  Documentation and analysis of the results  Collecting running data – Log File  Displaying results  For each test module, determining the number of iterations or the total running time.

8. Host Host - Lower layer Hyper Terminal  Procedure control – PPC  Part of Microsoft Windows  Serial port Xilinx Tools  JTAG – Load, control, configuration  XMD – monitoring the PPC, debugging – JTAG port – Part of EDK  Chip Scope – Internal logic analyzer

9. DUT DUT – Virtex II Pro (XC2VP7) Component list 44 18Kbit Block-RAMs 11K Configurable logic blocks (CLB) 44 18X18 bit multipliers 8 2.5 Gbps Rocket I/O transceivers 4 Digital Clock Manager units (DCM) Power-PC 405 CPU

10. Virtex II-Pro Overview - Platform Input: Push buttons, Dip Switches Output: User Led, LCD Input/Output: JTAG Port,System Ace, Parallel Cable, Cpu Trace Port Cpu Debug Port,Rocket I/O RS232 Port,Clock Generator P160 Module

11. Testing Techniques (1) The System  Contains the testing module and the tested module  Basic assumption: system under radiation will necessarily collapse  Error recovery ability - Tracking mechanism: Watch Dog (hardware/software) System Testing Module Tested Module

12. Testing Module  Self test ability. For example – TMR (or …)  Minimal involvement  Implementation: - Minimal resources usage - Based mainly on logic Testing Techniques (2) System Testing Module Tested Module

13. Testing Techniques (3) Tested Module  Maximal components’ mapping  EDC – Error Detection and Correction  Implementation - Unique test for each component of the device - Different tests will combine components used in typical applications - Initial test: configuration area and logic System Testing Module Tested Module

14. Final Goals  GUI as a combination of both static (previous project) and dynamic tests  Graphical display of errors vs. time

15. Design Tools ●HDL Designer (VHDL) – creating hardware applications ●ModelSim – VHDL simulation ●SynplifyPRO – synthesis tool ●Xilinx ISE – Place & Route ●EDK – PPC implementation ●Visual Basic – designing the GUI

16. General Schedule In the first semester, we will concentrate on the internal components of the device, developing and improving test algorithms. In the second semester, we will approach the processor (using EDK), and will test it using the knowledge we have acquired during the first part of the project.

17. Schedule – First Semester ●Learning VHDL design tools and other development tools ●Getting familiar with the V2P and its development environment ●Determine the test algorithms ●Creating the test vectors for each component