1. Foundation and XACTstepTM Software

2. XACTstepTM M1 Software ALLIANCE Series Software Backplane
Foundation Series
ALLIANCE Series
Software Backplane
Libraries and Interfaces for Leading EDA Vendors
Core Implementation Software - Map, Place, Route, Bitstream generation, and analysis
Complete, Ready-to-Use
Includes Schematic, Simulation, and VHDL Synthesis
Graphical User Interface is very similar to XACTStep v.6.0

3. Design Implementation
Design Tools
Standard CAE entry and verification tools
XACT software implements the design
The design is optimized for best performance and minimal size
Graphical User Interface and Command Line Interface
Easy access to other Xilinx programs
Manages and tracks design revisions
Functional Simulation
Back Annotation
Schematic,
HDL Code
Design Implementation
Simulation
Static Timing Analysis,
In-Circuit Testing
Design
Entry
Verification
XACT
Xilinx
Foundation
or Alliance

4. Multi-Source Integration Mixed-Level Flows
HDL
Schematic
Enables multiple sources and multiple EDA vendors in the same flow
Allows team development
Reduces design source translations
Design the way you are used to
Enables rapid, accurate iterations
Works well within existing ASIC flows
Facilitates Design Reuse
Existing Designs
Cores
Design Source Integration
EDIF
VHDL
Verilog
SDF
Standards Based
Check Point Verification
Knowledge
Driven Implementation

5. 3rd Party Support & Libraries
Xilinx 3rd Party Design Entry & Simulation Support
Synopsys, Cadence, Mentor Graphics, Aldec, Viewlogic
OrCad, Synplicity, Model Technologies, Synario, Exemplar, ABEL and others supply libs & interfaces
Industry standard file formats:
VHDL, Verilog, and EDIF netlist formats
SDF Standard Delay files
VITAL library support
Xilinx Libraries
Optimized components for use in any Xilinx FPGA or CPLD
Wide range of functions
Comparators, Arithmetic functions, memory
DSP and PCI interfaces
Easy to use with ABEL, VHDL, Verilog, schematic entry

6. Libraries, Macros & Attributes
Libraries are common design sets for all design entry tools (eg. text, schematic, Foundation, Synopsys, Viewlogic, etc.)
Library “interfaces” are specific to each front end
Attributes are library element properties
Online “Libraries Guide” has full listings and descriptions
Unified Libraries:
Boolean functions, TTL, Flip-Flops, Adders, RAM, small functions
LogiBlox Libraries:
Variable size blocks of adders, registers, RAM, ROM, etc.
Properties defined as attributes

7. Foundation Overview
Integrated Aldec front end and Xilinx implmentation tools
Aldec Project Manager can invoke Xilinx Design Manager and other tools
Optional VHDL synthesizer
All Windows-based
Aldec tools:
Schematic capture
Gate-level simulation
VHDL/ABEL Language Assistant
Includes Viewlogic schematic import feature
Includes on-line documentation and tutorials
Synopsys FPGA Express (VHDL, Verilog)
bundled package in1997

8. Foundation Project Manager
Offers access to Aldec or Xilinx tools
M1 Foundation Graphical User Interface very similar to v.6.0.x 2 1 4 3

9. Schematic Entry 1 2 3 6 7 4 5

10. ABEL and VHDL Text Entry
From schematic menu (or via HDL Editor), select Hierarchy -> New Symbol Wizard… to create symbol.
Select HDL Editor & Language Assistant to learn by example, then define block.
Synthesize to EDIF. 1 5 4 3 2

11. State Machine Graphical Editor
Graphical editor synthesizes into ABEL or VHDL code

12. Foundation Simulator
Simulation 1 2 4 5 3

13. Implementation - M1 Design Manager
Manages design data
Access reports
Supports CPLDs, FPGAs
Flow Engine
Timing Analyzer
PROM File Formatter
Hardware Debugger
EPIC Design Editor

14. Terminology
Project
Source file; has a defined working directory and family
Version
A Xilinx netlist translation of the schematic
Multiple Versions result from iterative schematic changes
Revision
An implementation of a Xilinx netlist
Multiple revisions typically result from different options
Part type
Specified at translation; can be changed in a new revision

15. Toolbox Programs Flow Engine
Controls start/stop points and custom options
Timing Analyzer
Report on net and path delays
PROM File Formatter
Create file to program configuration file into PROM
Hardware Debugger
Download configuration file
EPIC Design Editor
Device-level view of routing

16. Flow Engine View status of tools Control tool options
Implements design to the bitstream