1. 1 Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea Ismail Dept. of EECS, Northwestern Univ. SACTA: A Self-Adjusting Clock Tree Architecture to Cope with Temperature Variation

2. 2 Outline Introduction Motivation SACTA architecture skew buffer design optimization Experimental results Conclusion

3. 3 Introduction Temperature impacts affect transistor and interconnect delay cause timing violation Existing techniques temperature insensitive clock tree [1] robust clock scheduling [3] razor technology [4] each having pros and cons

4. 4 Introduction On-chip temperature variation input data dependent spatial and temporal variation hard to predict at design time dynamic architecture is highly desired Requirements small reaction time reasonable overhead

5. 5 Introduction On-chip temperature variation input data dependent spatial and temporal variation hard to predict at design time dynamic architecture is highly desired Requirements small reaction time reasonable overhead

6. 6 Introduction On-chip temperature variation input data dependent spatial and temporal variation hard to predict at design time dynamic architecture is highly desired Requirements small reaction time reasonable overhead

7. 7 Introduction On-chip temperature variation input data dependent spatial and temporal variation hard to predict at design time dynamic architecture is highly desired Requirements small reaction time reasonable overhead

8. 8 Motivation Motivation a one dimensional pipeline combinational logic blocks act like springs temperature acts like forces applied on the springs R1R1 R2R2 R3R3 θ /ºC x clk

9. 9 x Motivation Motivation a one dimensional pipeline combinational logic blocks act like springs temperature acts like forces applied on the springs what if the clock skews act like springs also? R1R1 R2R2 R3R3 clk θ /ºC

10. 10 Motivation Clock skews x i : clock signal arrival time at register R i D i,i+1 = T c-q +T logic(max) +T int +T setup d i,i+1 = T c-q +T logic(min) +T int +T hold Clock Skew Constraints – d i,i+1 ≤ x i – x i+1 ≤ T cp – D i,i+1 R1R1 R2R2 R3R3 clk setup time constraint hold time constraint

11. 11 Motivation Clock skew constraints – d i,i+1 ≤ x i – x i+1 ≤ T cp – D i,i+1 Observation d i,i+1, –(x i – x i+1 ) and D i,i+1 should be made to have the same dependency on temperature R1R1 R2R2 R3R3 clk

12. 12 Motivation How does d i,i+1 and D i,i+1 depend on temperature? HSPICE simulation v.s. linear model we only need to make the clock skews linearly dependant on temperature

13. 13 Motivation Constraints revisited assuming the operating temperature ranging between θ min and θ max the constraints form a quadrangle we only need to couple x i – x i ＋ 1 with the local temperature θ i,i+1, and make it a line lying strictly within the the quadrangle θ max tdtd T cp – D i,i+1 (θ i,i+1 ) – d i,i+1 (θ i,i+1 ) (x i – x i ＋ 1 )(θ i,i+1 ) θ min – d i,i+1 ≤ x i – x i+1 ≤ T cp – D i,i+1 θ

14. 14 Architecture SACTA: Architecture Self-Adjusting Clock Tree Architecture x i – x i+1 = (f i – f i+1 – s i ) + k i (Δθ), where Δθ = θ max – θ Automatic Temperature Adjustable (ATA) skew buffer Temperature-insensitive (fixed) skew buffer f1f1 fifi f i+1 fnfn RiRi R i+1 RnRn R1R1 s 1 -k 1 Δθs i -k i Δθs i+1 -k i+1 Δθ clk

15. 15 SACTABuffer SACTA: Skew Buffer Design Fixed skew buffer bias the gates to Zero Temperature Coefficient point V ZTC V dd M1M1 M2M2 M3M3 M4M4 I ZTC V ZTC + – V ZTC Ref min-size V ZTC Fixed Skew Buffer W min, [L min, 5L min ]

16. 16 ATA skew buffer SACTA: Skew Buffer Design Fixed Buffers V dd V ZTC Ref min-size W min, [L min, 5L min ]

17. 17 SACTAOptimization SACTA: Optimization Optimizing the clock tree f i and s i positively related to the overhead minimizing the sum of f i and s i Constraints skew buffer design constraints: s i ≥ s min, f i ≥ f min, k i – λs i = 0 timing correctness: for θ = θ max, θ min, –d i,i+1 (θ)≤(x i –x i+1 )(θ)≤T cp – D i,i+1 (θ) tdtd T cp – D i,i+1 (θ i,i+1 ) – d i,i+1 (θ i,i+1 ) (x i – x i ＋ 1 )(θ i,i+1 ) θ min θ max

18. 18 SACTA optimization formulation SACTAOptimization SACTA: Optimization M INIMIZE Σ s i + Σ f i s.t. f i – s i – f i+1 ≤ T cp – D i,i+1 f i – s i – f i+1 ≥ – d i,i+1 f i – s i + k i Δθ M – f i+1 ≤ T cp – D i,i+1 + Γ i,i+1 Δθ M f i – s i + k i Δθ M – f i+1 ≥ – d i,i+1 + γ i,i+1 Δθ M k i – λs i = 0 s i ≥ s min, f i, f i+1 ≥ f min i = 1, 2, …, n-1

19. 19 Transforming the problem into a network flow formulation defining four new variables f i Δ = f i – f min s i Δ = s i – s min u i = f i – s i – f i+1 + d i,i+1 v i = f i – s i (1-λΔθ M ) – f i+1 + d i,i+1 – γ i,i+1 Δθ M the optimization problem can be rewritten as Optimization SACTA: Optimization

20. 20 Optimization SACTA: Optimization M INIMIZE Σs i Δ + Σf i Δ s.t. – f i Δ + s i Δ + f i+1 Δ + u i = d i,i+1 + s min – (λΔθ M )s i Δ – u i + v i = – γ i,i+1 Δθ M – (λΔθ M ) s min 0 ≤ u i ≤ T cp – D i,i+1 + d i,i+1 0 ≤ v i ≤ T cp – D i,i+1 + d i,i+1 + (Γ i,i+1 – γ i,i+1 )Δθ M s i Δ, f i Δ, f i+1 Δ ≥ 0 i = 1, 2, …, n-1 Generalized min-cost flow formulation Balanced Condition Bounds on the Flows

21. 21 Optimization SACTA: Optimization Balance Condition: – f i Δ + s i Δ + f i+1 Δ + u i = d i,i+1 + s min – (λΔθ M )s i Δ – u i + v i = – γ i,i+1 Δθ M – (λΔθ M ) s min Graph based depiction of the constraints 0, T cp – D i,i+1 + d i,i+1, u i 1, +∞, f i Δ 1, +∞, f i+1 Δ pipi qiqi cost, capacity, flow pq 1, +∞, s i Δ 0, T cp – D i,i+1 +d i,i+1 +(Γ i,i+1 – γ i,i+1 ) Δθ M, v i Bounds on the Flows: 0 ≤ v i ≤ T cp – D i,i+1 + d i,i+1 + (Γ i,i+1 – γ i,i+1 )Δθ M 0 ≤ u i ≤ T cp – D i,i+1 + d i,i+1 s i Δ, f i Δ, f i+1 Δ ≥ 0

22. 22 Optimization SACTA: Optimization Graph based depiction of the constraints 0, T cp – D i,i+1 + d i,i+1, u i cost, capacity, flow 1, +∞, f i Δ 1, +∞, f i+1 Δ pipi qiqi pq 1, +∞, s i 0, T cp – D i,i+1 +d i,i+1 +(Γ i,i+1 – γ i,i+1 ) Δθ M, v i p n-1 q n-1 p1p1 p2p2 p3p3 q1q1 q2q2 q3q3 w

23. 23 Experimental Results Experiments six different systolic pipelines both balanced and unbalanced pipelines are examined targeting range θ max = 125 ºC, θ min = 25 ºC

24. 24 Experimental Results Experimental results uniform temperature distribution maximum permissible temperature six different pipelines T/°C

25. 25 Experimental Results Experimental results uniform temperature distribution (125 ºC) relative performance improvement six different pipelines RP

26. 26 Experimental Results Experimental results various temperature profiles X: timing error, Y: no timing error Thermal Profile/ºCPipelines w/o SACTAPipelines w/ SACTA s1s1 s2s2 s3s3 s4s4 s5s5 PBPURBRUFBFUPBPURBRUFBFU 125115110107105XXXXXXYYYYYY 107110115125XXYYXXYYYYYY 100105110105100XXYYXXYYYYYY 135125120117115XXXXXXXYXYXY 117120125135XXXXXXXYXXXX

27. 27 Experimental Results Experimental results hardware overhead PBPURBRUFBFU On-Tree Inv Num675167506753 Pipeline Cell Num2082 1572 498

28. 28 Conclusions Temperature variation affects circuit timing Dynamic architectures are required SACTA architecture, skew buffer design, optimization SACTA enhances system robustness and performance hardware overhead of SACTA is small

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