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CS 7810 Lecture 15 A Case for Thermal-Aware Floorplanning at the Microarchitectural Level K. Sankaranarayanan, S. Velusamy, M. Stan, K. Skadron Journal.

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Presentation on theme: "CS 7810 Lecture 15 A Case for Thermal-Aware Floorplanning at the Microarchitectural Level K. Sankaranarayanan, S. Velusamy, M. Stan, K. Skadron Journal."— Presentation transcript:

1 CS 7810 Lecture 15 A Case for Thermal-Aware Floorplanning at the Microarchitectural Level K. Sankaranarayanan, S. Velusamy, M. Stan, K. Skadron Journal of ILP, October 2005

2 Importance of Temperature High power density  cooling tech must improve Every additional watt increases chip’s cooling/packaging cost by $4 Higher temperature  exponentially higher leakage Temperature variations cause wear and tear

3 General Approaches Reduce overall power consumption Wait for some unit to reach temperature limit and then throttle back (dynamic thermal management) Better floorplans so that heat is evenly distributed and likelihood of local hotspot is reduced Better floorplanning does not eliminate the need for DTM

4 Thermal Modeling Thermal resistance: models the rate at which heat passes through Thermal capacity: models the temperature rise because of heat absorption Resistance  thickness / area Capacitance  thickness x area

5 Models for Alpha-like Processor

6 Effect of Lateral Spreading Thermal resistance = 0Thermal resistance = infinity

7 Simulation Setup Ambient temperature of 40 o C Trigger threshold (when DTM is invoked) 111.8 o C Emergency threshold is 115 o C Alpha core is 6.2mm x 6.2mm – cross-core latency is 4.21 and 7.16 cyc (on different metal layers) L2 cache is wrapped around the core to form a square

8 Simulated Annealing In each iteration, perturb the solution with a probability that equals the difference between the “quality” of current and optimal solution What is the metric for “quality”? ( A + W ) T W =  c ij d ij A is area – some layouts increase the amount of white space W is the performance penalty becoz of wire delays T is peak temperature for the layout d is the distance between units in cyc c reflects the performance impact of that distance

9 Inputs to Algorithm Profile a subset of benchmarks to estimate power density of each block Profile the performance impact of each set of wire delays to determine weights

10 Wire Delay Penalties

11 Optimal Floorplans Flp-basic each wire delay gets an equal weight Flp-advanced wire delays are weighted Dead space 1.14% 5.24% Total wire length is longer here

12 Impact on Peak Temperature Additional temp. reduction becoz of poorer IPC and lower leakage

13 Comparison with DTM (DVS) DVS: Assumes 10  s overhead for a change DVS-i: Assumes no overhead for a change Emergency threshold

14 Title Bullet

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