1. CS 258 Parallel Computer Architecture Lecture 8 Network Interface Design February 20, 2008 Prof John D. Kubiatowicz http://www.cs.berkeley.edu/~kubitron/cs258

2. Lec 8.2 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Network Transaction Primitive one-way transfer of information from a source output buffer to a dest. input buffer –causes some action at the destination –occurrence is not directly visible at source deposit data, state change, reply

3. Lec 8.3 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Programming Models Realized by Protocols CAD MultiprogrammingShared address Message passing Data parallel DatabaseScientific modeling Parallel applications Programming models Communication abstraction User/system boundary Compilation or library Operating systems support Communication hardware Physical communication medium Hardware/software boundary Network Transactions

4. Lec 8.4 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Shared Address Space Abstraction Fundamentally a two-way request/response protocol –writes have an acknowledgement Issues –fixed or variable length (bulk) transfers –remote virtual or physical address, where is action performed? –deadlock avoidance and input buffer full coherent? consistent?

5. Lec 8.5 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Consistency write-atomicity violated without caching –No way to enforce serialization Solution? Acknowledge write of A before writing Flag… P3P3 P2P2 P1P1

6. Lec 8.6 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Properties of Shared Address Abstraction Source and destination data addresses are specified by the source of the request –a degree of logical coupling and trust no storage logically “outside the address space” »may employ temporary buffers for transport Operations are fundamentally request response Remote operation can be performed on remote memory –logically does not require intervention of the remote processor

7. Lec 8.7 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Message passing Bulk transfers Complex synchronization semantics –more complex protocols –More complex action Synchronous –Send completes after matching recv and source data sent –Receive completes after data transfer complete from matching send Asynchronous –Send completes after send buffer may be reused

8. Lec 8.8 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Synchronous Message Passing Constrained programming model. Deterministic! What happens when threads added? Destination contention very limited. User/System boundary? Processor Action?

9. Lec 8.9 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Asynch. Message Passing: Optimistic More powerful programming model Wildcard receive => non-deterministic Storage required within msg layer?

10. Lec 8.10 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Asynch. Msg Passing: Conservative Where is the buffering? Contention control? Receiver initiated protocol? Short message optimizations

11. Lec 8.11 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Features of Msg Passing Abstraction Source knows send data address, dest. knows receive data address –after handshake they both know both Arbitrary storage “outside the local address spaces” –may post many sends before any receives –non-blocking asynchronous sends reduces the requirement to an arbitrary number of descriptors »fine print says these are limited too Optimistically, can be 1-phase transaction –Compare to 2-phase for shared address space –Need some sort of flow control »Credit scheme? More conservative: 3-phase transaction –includes a request / response Essential point: combined synchronization and communication in a single package!

12. Lec 8.12 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Active Messages User-level analog of network transaction –transfer data packet and invoke handler to extract it from the network and integrate with on-going computation Request/Reply Event notification: interrupts, polling, events? May also perform memory-to-memory transfer Request handler Reply

13. Lec 8.13 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Common Challenges Input buffer overflow –N-1 queue over-commitment => must slow sources Options: –reserve space per source(credit) »when available for reuse? Ack or Higher level –Refuse input when full »backpressure in reliable network »tree saturation »deadlock free »what happens to traffic not bound for congested dest? –Reserve ack back channel –drop packets –Utilize higher-level semantics of programming model

14. Lec 8.14 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 The Fetch Deadlock Problem Even if a node cannot issue a request, it must sink network transactions! –Incoming transaction may be request  generate a response. –Closed system (finite buffering) Deadlock occurs even if network deadlock free! NETWORK

15. Lec 8.15 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Solutions to Fetch Deadlock? logically independent request/reply networks –physical networks –virtual channels with separate input/output queues bound requests and reserve input buffer space –K(P-1) requests + K responses per node –service discipline to avoid fetch deadlock? NACK on input buffer full –NACK delivery? Alewife Solution: –Dynamically increase buffer space to memory when necessary –Argument: this is an uncommon case, so use software to fix

16. Lec 8.16 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Network Transaction Processing Key Design Issue: How much interpretation of the message? How much dedicated processing in the Comm. Assist? PM CA PM ° ° ° Scalable Network Node Architecture Communication Assist Message Output Processing – checks – translation – formating – scheduling Input Processing – checks – translation – buffering – action

17. Lec 8.17 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Spectrum of Designs None: Physical bit stream –blind, physical DMAnCUBE, iPSC,... User/System –User-level portCM-5, *T, Alewife –User-level handlerJ-Machine, Monsoon,... Remote virtual address –Processing, translationParagon, Meiko CS-2 Global physical address –Proc + Memory controllerRP3, BBN, T3D Cache-to-cache –Cache controllerDash, Alewife, KSR, Flash Increasing HW Support, Specialization, Intrusiveness, Performance (???)

18. Lec 8.18 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Net Transactions: Physical DMA DMA controlled by regs, generates interrupts Physical => OS initiates transfers Send-side –construct system “envelope” around user data in kernel area Receive –must receive into system buffer, since no interpretation in CA senderauth dest addr

19. Lec 8.19 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 nCUBE Network Interface independent DMA channel per link direction –leave input buffers always open –segmented messages routing interprets envelope –dimension-order routing on hypercube –bit-serial with 36 bit cut-through Os16 ins 260 cy13 us Or18200 cy15 us - includes interrupt

20. Lec 8.20 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Conventional LAN NI NIC Controller DMA addr len trncv TX RX Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Addr Len Status Next Data Host Memory NIC IO Bus mem bus Proc Costs: Marshalling, OS calls, interrupts

21. Lec 8.21 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 User Level Ports initiate transaction at user level deliver to user without OS intervention network port in user space –May use virtual memory to map physical I/O to user mode User/system flag in envelope –protection check, translation, routing, media access in src CA –user/sys check in dest CA, interrupt on system

22. Lec 8.22 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Example: CM-5 Input and output FIFO for each network 2 data networks tag per message –index NI mapping table context switching? Alewife integrated NI on chip *T and iWARP also Os50 cy1.5 us Or53 cy1.6 us interrupt10us

23. Lec 8.23 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 User Level Handlers Hardware support to vector to address specified in message –On arrival, hardware fetches handler address and starts execution Active Messages: two options –Computation in background threaads »Handler never blocks: it integrates message into computation –Computation in handlers (Message Driven Processing) »Handler does work, may need to send messages or block User/system P Mem DestDataAddress P Mem 

24. Lec 8.24 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 J-Machine Each node a small mdg driven processor HW support to queue msgs and dispatch to msg handler task

25. Lec 8.25 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Alewife Messaging Send message –write words to special network interface registers –Execute atomic launch instruction Receive –Generate interrupt/launch user-level thread context –Examine message by reading from special network interface registers –Execute dispose message –Exit atomic section

26. Lec 8.26 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 iWARP Nodes integrate communication with computation on systolic basis Msg data direct to register of neighbor Stream into memory Interface unit Host

27. Lec 8.27 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Sharing of Network Interface What if user in middle of constructing message and must context switch??? –Need Atomic Send operation! »Message either completely in network or not at all »Can save/restore user’s work if necessary (think about single set of network interface registers –J-Machine mistake: after start sending message must let sender finish »Flits start entering network with first SEND instruction »Only a SENDE instruction constructs tail of message Receive Atomicity –If want to allow user-level interrupts or polling, must give user control over network reception »Closer user is to network, easier it is for him/her to screw it up: Refuse to empty network, etc »However, must allow atomicity: way for good user to select when their message handlers get interrupted –Polling: ultimate receive atomicity – never interrupted »Fine as long as user keeps absorbing messages

28. Lec 8.28 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Dedicated processing without dedicated hardware design

29. Lec 8.29 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Dedicated Message Processor General Purpose processor performs arbitrary output processing (at system level) General Purpose processor interprets incoming network transactions (at system level) User Processor Msg Processor share memory Msg Processor Msg Processor via system network transaction Network ° ° ° dest Mem P M P NI UserSystem Mem P M P NI UserSystem

30. Lec 8.30 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Levels of Network Transaction User Processor stores cmd / msg / data into shared output queue –must still check for output queue full (or make elastic) Communication assists make transaction happen –checking, translation, scheduling, transport, interpretation Effect observed on destination address space and/or events Protocol divided between two layers Network ° ° ° dest Mem P M P NI UserSystem Mem P M P NI

31. Lec 8.31 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Example: Intel Paragon

32. Lec 8.32 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 User Level Abstraction (Lok Liu) Any user process can post a transaction for any other in protection domain –communication layer moves OQ src –> IQ dest –may involve indirection: VAS src –> VAS dest See, for instance: –“Remote Queues: Exposing Message Queues for Optimization and Atomicity,” Eric A. Brewer, Fredrik T. Chong, Lok T. Liu, Shamik D. Sharma, John D. Kubiatowicz, SPAA 1995 Proc OQ IQ VAS Proc OQ IQ VAS Proc OQ IQ VAS Proc OQ IQ VAS

33. Lec 8.33 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Msg Processor Events Dispatcher User Output Queues Send FIFO ~Empty Rcv FIFO ~Full Send DMA Rcv DMA DMA done Compute Processor Kernel System Event

34. Lec 8.34 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Basic Implementation Costs: Scalar Cache-to-cache transfer (two 32B lines, quad word ops) –producer: read(miss,S), chk, write(S,WT), write(I,WT),write(S,WT) –consumer: read(miss,S), chk, read(H), read(miss,S), read(H),write(S,WT) to NI FIFO: read status, chk, write,... from NI FIFO: read status, chk, dispatch, read, read,... CP User OQ MP Registers Cache Net FIFO User IQ MPCP Net 21.52 4.4 µs5.4 µs 10.5 µs 7 wds 222 250ns + H*40ns

35. Lec 8.35 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Virtual DMA -> Virtual DMA Send MP segments into 8K pages and does VA –> PA Recv MP reassembles, does dispatch and VA –> PA per page CP User OQ MP Registers Cache Net FIFO User IQ MP CP Net 21.52 7 wds 222 Memory sDMA hdr rDMA MP 2048 400 MB/s 175 MB/s 400 MB/s

36. Lec 8.36 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Single Page Transfer Rate Actual Buffer Size: 2048 Effective Buffer Size: 3232

37. Lec 8.37 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Msg Processor Assessment Concurrency Intensive –Need to keep inbound flows moving while outbound flows stalled –Large transfers segmented Reduces overhead but adds latency User Output Queues Send FIFO ~Empty Rcv FIFO ~Full Send DMA Rcv DMA DMA done Compute Processor Kernel System Event User Input Queues VAS Dispatcher

38. Lec 8.38 2/20/08Kubiatowicz CS258 ©UCB Spring 2008 Conclusion Shared Address Space –Request/Response Protocol –Global names for memory locations specify nodes Many different Message-Passing styles –Global Address space: 2-way –Optimistic message passing: 1-way –Conservative transfer: 3-way “Fetch Deadlock” –Request  Response introduces cycle through network –Fix with: »2 networks »dynamic increase in buffer space Network Interfaces –User-level access –DMA –Atomicity